Abstract: An improved sense amplifier for a computer having non-volatile memories, each non-volatile memory having an array of memory cells, each cell having a drain, and the drains of all the cells for one column of cells connected to a drain-column line, The sense amplifier reads the state of the memory cell by a) sensing a reference current; b) providing drain-column voltage swings during the reference current sensing; c) sensing the current on the drain-column line; d) producing voltages above and below a reference voltage whereas the produced voltages represent the state of the memory cell; and, e) adjusting the bias of the biasing transistors in response to the produced voltages.

Abstract: A polarity-convertible Josephson driver circuit includes first and second driving voltage generating circuits, a driven line, and a load resistor. Each of the first and second driving voltage generating circuits has a loop circuit for forming at least one loop, the loop circuit being constituted by inductances and Josephson junctions so that a plurality of series-connected circuits each constituted by the inductances and the Josephson junctions are parallelly connected between an output point and a reference point, and a control line which has one terminal connected to an input point and the other terminal connected to the output point and is arranged to magnetically coupled to the loop circuit. The driven line connects the output points of the first and second driving voltage generating circuits to each other. A load resistor is inserted in the driven line.

Abstract: A row address decoder and word line driver unit selectively drives a word line selected from one of a plurality sets of word lines, and comprises a plurality of row address decoders and word line driver sub-units for selecting a set of word lines and a plurality of address decoder sub-units for selecting a word line from the selected set of word lines, wherein a pair of p-channel enhancement type transfer transistors coupled between a selected row address decoder and word line driver unit and the selected word line are switched by a selected address decoder sub-unit for supplying a word line driving signal, the complementary word line driving signal switches an n-channel enhancement type first pull-down transistor coupled between the selected word line and a ground voltage line, and the selected address decoder sub-unit further switches an n-channel enhancement type second pull-down transistor, thereby charging to and discharging from the selected word line through the transistors operable in the saturation r

Abstract: Clock pulses from a master oscillator are distributed in a multiprocessor computer system so that they arrive at a large number of utilization points located in operating clusters of modules within extremely tight time tolerances of each other. The delays associated with each component, electrical or optical connection, cable or the like are determined by direct measurement or by using known standard characteristics. A time delay budget for each complete clock pulse path from the point of initial divergence from the master clock source to the final chip delivery point is logged and summed. Components capable of introducing predetermined amounts of time delay are incorporated in some or all clock pulse paths. These components are adjusted so as to balance out the differences determined from the clock path budgets. The clock paths are implemented in electrical components either alone or in combination with optical components, or in substantially all optical configurations.

Abstract: A reader comprises a feeding path for boarding pass to be inserted in various orientations, pairs of feeding rollers for transporting the boarding pass along the path, and four sensor units arranged along the path each for sensing a signal recorded on the boarding pass inserted in a particular orientation.

Abstract: A Read-Only semiconductor memory cell includes: a semiconductor substrate and a source and a drain formed on one surface of the substrate; a channel region, which is in between source and drain regions on the surface of the substrate, is controlled by X-control gate XCG and Y-control gate YCG which are formed on the surface of the substrate and isolated from each other and from source and drain regions and from semiconductor substrate through insulating films. Multiple levels of threshold voltages of the cells exist for ROM codes. The cell structure provide a means for accurate cell current during read, and is simpler for peripheral control circuit design and is contactless, fieldless, suitable for high reliable Mega-bit memory devices.

Abstract: A semiconductor memory device has a device for reading stored information out of a memory element of a semiconductor by applying a reading voltage onto a word line; and a single word line clamping circuit for controlling the reading voltage applied onto the word line such that the reading voltage is close to a relatively high threshold voltage of the memory element when the reading voltage is applied onto the word line, the word line clamping circuit being commonly disposed on a plurality of word lines.

Abstract: A memory (50) having a BICMOS sense amplifier (20) includes a differential amplifier stage (11), emitter-follower input transistors (25 and 26), and emitter-follower output transistors (27 and 28). When sense amplifier (20) is deselected, P-channel transistors (31-37) pull the bases of the bipolar transistors (23-28) to V.sub.DD -2V.sub.BE and P-channel transistors (29 and 30) decouple the bases of emitter-follower output transistors (27 and 28) from the collectors of transistors (23 and 24). At the same time, N-channel transistors (38, 40, 42, 44, and 46) decouple N-channel transistors (39, 41, 43, 45, and 47) from the emitters of bipolar transistors (23-28). Thus, no current can flow, reducing the power consumption of sense amplifier (20). Also, bipolar transistors (23-28) are prevented from being excessively reverse-biased. Additionally, a plurality of sense amplifiers (20) can have their outputs wired-OR connected.

Abstract: A scan pattern generator for use in a bar code reader which uses a single drive (one coil and one magnet) to produce movement of a reflective surface so as to produce an oscillating movement of the surface in two directions, thereby forming a raster-type scanning pattern when a light beam is reflected off the surface.

Abstract: A write enable buffer circuit for generating an internal write designating signal includes a gate circuit for inhibiting generation of the signal in response to an internal output designating signal which attains a settled state prior to a data outputting operation by a data outputting buffer. In data reading, the gate circuit forbids generation of an internal write designating signal to certainly hold the internal write designating signal in a disable state even if a noise is generated in data output. Thus, it is prevented that an internal write designating signal is erroneously generated due to noise in data output to bring data output buffer into an output high impedance state, and also the data input buffer is certainly maintained at an inactive state in data output.

Abstract: SRAM comprises a word line driving circuit selecting a predetermined number of word lines in accordance with an input address at the time of a normal operation, and simultaneously selecting all word lines or word lines, which are more than the number of word lines to be selected at the time of the normal operation, at the time of a voltage stress applying test, and a bit line load circuit applying a predetermined bias voltage to said pair of bit lines at the time of the normal operation, and controlling the bias voltage not to be applied to at least one of said pair of bit lines or applying the bias voltage, which is lower than the bias voltage at the time of the normal operation, at the time of the voltage stress test.

Abstract: A hybrid open/folded bit line sense amplifier arrangement and accompanying circuitry primarily for use on a ULSI DRAM memory chip to reduce the area needed for a memory cell and eliminate noise between bit lines. The circuitry includes two memory arrays containing a plurality of memory cells interconnected by a plurality of bit lines and word lines. In the preferred embodiment, the memory cells are accessible on every two out of three bit lines encountered by a word line. A set of open bit line sense amplifiers each with two connectors, one multiplexed to a number of bit lines in the first array and the other multiplexed to a number of bit lines in the second array is provided. Each memory array has a set of folded bit line sense amplifiers with two connectors each connector multiplexed to a number of bit lines in the array. The control circuitry with multiplexing ensures that the connectors of the sense amplifiers access only one bit lines at a time.

Abstract: A wagering system for random drawing lotteries has a central data processor managing acceptance of player entries and payout authorization. Remote agent terminals receive player entry data from players and process authorized payouts. Portable agent data modules having an on-board memory and security provisions are issued to the agents and carry data in both directions between the central data processor and the terminals. Preferably the agent modules are integrated circuit cards or "smartcards". Available player entries are downloaded from the central data processor to the agent data modules, stored on the agent data modules for transport to the agent data terminals, and uploaded under security protection to the agent data terminals when processing a wager. The agent data modules record assignment of the available player entries to players for reporting to the central processor and can obtain payout authorizations or credits.

Abstract: A divided word line driving circuit applicable to a static random access memory (SRAM) employing a divided word line method is disclosed. When a divided word line is activated, the potential at the input of an inverter for driving the word line is brought to a low level. When the input signals S1 and S2 are both at a low level, the divided word line is brought to an inactive state. The input of the inverter is charged by a transistor 101 in addition to a transistor 102 which is always on. In other words, transistor 101 contributes to accelerating charging of the input of the inverter. Consequently, the potential of the divided word line is made to rise at high speed, so that access operation at high speed can be achieved. The circuit is implemented with a small number of transistors, so that it becomes also possible to enhance the degree of integration of a SRAM.

Abstract: Methods and apparatuses are disclosed for improving accuracy of recording and reproducing information onto and from a magneto-optic recording information medium. In the first method, a width of a mark formed by a relatively low intensity light beam between two kinds of light beam intensities used for recording information is made larger than a sum of a track land width and the maximum track offset of the light beam, thereby the mark formed by the relatively low intensity light beam covers the track land portion in its full width. In the first apparatus, a reflected light beam from the magneto-optic recording information medium is split into a reflected beam for information reproducing and a reflected beam for tracking and focusing servos at the reproducing, thereby the apparatus can remove part being affected by the track groove portion from the reflected light beam for information reproducing.

Abstract: A magnetic field of a polarity corresponding to information to be recorded is applied while a recording spot having a high energy is irradiated to a magneto-optical recording medium to record domains representing the information along a track. The recorded domains are read out by a reproducing spot having a lower energy than the recording spot and a high resolution power along the track.

Abstract: The endurance of ferroelectric capacitors can be extended by refreshing the ferroelectric material. The ferroelectric material is refreshed by impressing a voltage across the ferroelectric capacitor, which voltage is higher than that which the capacitor experiences during normal operation. A memory array having ferroelectric capacitive cells can be refreshed by first reading the memory cells, temporarily storing the data in associated sense amplifiers, refreshing the memory cells by impressing a higher-than-normal voltage across the ferroelectric cell capacitors, then rewriting the temporarily stored data back into the memory cells. Refresh circuits connected between the drive line and bit line common to a number of cells are driven with voltages which are higher than the memory cell experiences during normal read operations. A V.sub.cc to ground pulse train is applied to the drive line, while an inverted waveform thereof is applied to the bit line during refresh operations.

Abstract: A promotional device requiring customer interaction is presented comprising a removable, tamper-resistant housing with a slot in the housing for accepting an encoded substrate. The substrate has a coded area and a validation area. An electromechanical assembly located within the housing comprises means for aligning the substrate, means for scanning the encoded area of the substrate, and means for validating the substrate in the validation area.

Abstract: The disclosure concerns memory cards and, more particularly, cards that are used as means of prepayment in installations for the dispensing of products and services. It is proposed to make the memory rechargeable by means of a credit counter, incrementable from outside the card, and a comparator which compares the content of this counter with that of a page counter. The page counter records the number of pages of P accounting units already used up. A no more credit signal is emitted on an external terminal when the content of the page counter reaches the content of the credit counter. A security system against the fraudulent recharging of the card is set up by an algorithm bringing into play the content of the credit counter and an identification number contained in the card.

Abstract: A dynamic memory cell includes a first MOS transistor for data transfer connected at one end to a read/write node and having a gate connected to a transfer gate control line, a second MOS transistor having a gate connected to a first storage node on the other end side of the first MOS transistor and a gate capacitor used as a data storage capacitor, a third MOS transistor for refresh current supply connected at one end to the first storage node, and a resistor element or switching element connected between the gate of the third MOS transistor and the other end of the second MOS transistor. The cell itself has the refresh current supplying capability and it is not necessary to effect the refresh operation on the read/write node side by turning on the charge transfer transistor.