Abstract: This invention optimizes non-shared accesses and avoids dependencies across coherent endpoints to ensure bandwidth across the system even when sharing. The coherence controller is distributed across all coherent endpoints. The coherence controller for each memory endpoint keeps a state around for each coherent access to ensure the proper ordering of events. The coherence controller of this invention uses First-In-First-Out allocation to ensure full utilization of the resources before stalling and simplicity of implementation. The coherence controller provides Snoop Command/Response ID Allocation per memory endpoint.

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

Abstract: Disclosed herein are methods and apparatuses for requesting and obtaining data, in which time information is generated by use of a first device, and a data request command requesting data output by a second device is generated at a time point indicated by the time information. The generated data request command is transmitted, wherein the data request command includes the time information.

Abstract: An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.

Abstract: Devices, systems, and methods are described for allowing rules that are applied to one device to be applied to another device based on a user's interaction with only the devices. A rule-copy action, such as simultaneous shaking of the two devices, proximity of the two devices to each other, and/or the relative positions of the two devices, may be detected at one of the devices (e.g., a first device to which the user desires the rules or a copy of the rules to apply). In response to the rule-copy action, another device (e.g., a second device configured to operate according to the at least one rule) may be identified. The at least one rule may then be caused to be applied to the first device in response to detection of the rule-copy action, so as to configure the first device to operate according to the at least one rule.

Abstract: A rack with a mounting bay to accommodate servers, wherein 1) the mounting bay defines two opposing internal areas disposed parallel to an insertion direction of the servers and divided into a multiplicity of slots, 2) one or more data lines for data connection of servers are configured in the rack, 3) the data lines include optical data lines, and 4) on at least one of the two internal areas of the mounting bay, an end section of a data line with a data interface is disposed on each slot such that a contactless optical data connection to a further data interface on a corresponding server is enabled.

Abstract: A system, device and method for communicating between a host device and a plurality of peripheral devices wherein the communications utilize a single interface that is supported by the host. The host includes a plurality of class drivers and miniport drivers. Each of the class drivers implements functionality associated with one or more of the plurality of peripheral devices. Each miniport driver provides an interface by which one or more of the class drivers communicate with one or more of the plurality peripheral devices using class protocols, wherein the miniport drivers communicate through a single host interface supported by the host. An embedded controller interfaces with the plurality of peripheral devices using the respective native bus protocols of the peripheral devices and wherein the embedded controller interfaces with the plurality of miniport drivers using the single host interface.

Abstract: A master-slave detection method includes: every single time period, utilizing a random manner for determining whether a first device is used to transmit a specific pulse signal to a second device; every single time period, utilizing a random manner for determining whether the second device is used to transmit the specific pulse signal to the first device; when the first device receives at least one portion of the specific pulse signal earlier than the second device, setting the first device as a master device, stopping the master device from sending the specific pulse signal and utilizing the master device to start transmitting a specific sequence; and setting the second device as a slave device when the second device receives the specific sequence. The at least one portion of the specific pulse signal includes continuous single pulses.

Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.

Abstract: A hierarchical cache structure includes at least one real indexed higher level cache with a directory and a unified cache array for data and instructions, and at least two lower level caches, each split in an instruction cache and a data cache. An instruction cache of a split real indexed second level cache includes a directory and a corresponding cache array connected to the real indexed third level cache. A data cache of the split second level cache includes a directory connected to the third level cache. An instruction cache of a split virtually indexed first level cache is connected to the second level instruction cache. A cache array of a data cache of the first level cache is connected to the cache array of the second level instruction cache and to the cache array of the third level cache. A directory of the first level data cache is connected to the second level instruction cache directory and to the third level cache directory.

Abstract: Methods and apparatus, including computer program products, are provided for serial communications over a communications control pin. The method may include detecting, by a first device including a data interface, a current flow at a first communication control pin at the data interface; and assigning, by the first device based on the detection of the current flow at the first communication control pin, serial data communication circuitry to a second communication control pin at the data interface to carry serial data communications to another device. Related apparatus, systems, methods, and articles are also described.

Abstract: The present disclosure is directed to multi-protocol peripheral device communication. A method involves establishing a network connection between a management computing device and a peripheral device. The network connection utilizes a particular transport protocol. The method also involves generating, at the management computing device, a first message that represents a request for information from a peripheral device. The first message is in a format compatible with a first application protocol. The method further involves generating, at the management computing device, a second message based on the first message. The second message is in a format compatible with a second application protocol. The second application protocol is configured to communicate over the particular transport protocol. Additionally, the method involves transmitting, by the particular transport protocol, the second message from the management computing device to the peripheral device.

Abstract: An input system includes a communication device and a first input device. The communication device includes a communication chip and a communication port. The first input device includes a signal port connectable with the communication port and a device connecting port connectable with a second input device. In an input method, the communication device transmits a first pairing signal to the first input device so as to acquire a first identification code and a connection information of the first input device, and then the communication device transmits a first inquiring signal containing the first identification code to the first input device so as to acquire a first input signal from the first input device. If a second pairing signal and a second inquiring signal are transmitted to the second input device, the communication device acquires a second input signal from the second input device.

Abstract: According to an embodiment, an information processing device is connectable to a peripheral device and includes a buffer, a first operating system, a second operating system, and a monitor. The monitor is configured to enable the first operating system or the second operating system to execute in a switching manner. The monitor includes a switching controller that, when the second operating system issues an access request to the peripheral device, saves a state of the second operating system and suspends its execution as well as restores a state of the first operating system and restarts its execution. The first operating system includes a request input-output controller that reads the access request from the buffer, that divides the read access request into instructions in receivable units for the peripheral device, and that issues each instruction. The first operating system includes an access controller that accesses the peripheral device according to the instructions.

Abstract: A memory controller controlling a nonvolatile memory device having a plurality of memory blocks as a data storage space includes an error detection and correction circuit and a reclaim control unit. The error detection and correction circuit receives data from a memory block and calculates a comparison result by comparing a bit error rate of the received data and a predetermined value. The reclaim control unit determines whether or not to perform a read reclaim operation depending on the comparison result and a read voltage used to read the data. The read reclaim operation copies the data to a memory block different from a memory block having stored the data.

Abstract: A method of generating interaction activity information, performed by a device, is provided. The method includes establishing communication with at least one external apparatus; receiving first information about a user selectable function of the external apparatus; and generating second information, based on the first information, about a user selectable function of the device, wherein the user selectable function of the device corresponds to the user selectable function of the external device and can be performed in collaboration with the external device.

Abstract: Disclosed herein are several methods and systems for handling atomic write commands that reach scattered address ranges. One embodiment includes a method of performing an operation in a data storage device, the method comprising: receiving an atomic write command; obtaining a plurality of ranges of logical addresses affected by the atomic write command; for each of the plurality of affected ranges, assigning metadata information to track completion of a write operation performed at that range; performing the write operations in the ranges of logical addresses; updating the metadata information upon completion of the write operations in the ranges; and deferring an update to a translation map of the data storage device until the metadata information has been updated.

Abstract: A storage controller system may include a host controller that queues host commands as data transfer commands in a plurality of queue channels. The storage controller system may also include a data storage controller that selects data transfer commands for execution. The data storage controller may select all data transfer commands associated with a host command when all of the data transfer commands are located at heads of the queue channels. Alternatively, the data storage controller may select for execution data transfer commands at heads of the queue channels when associated cache areas are available to receive data, regardless of whether all of the data transfer commands associated with a host command are at the heads. The host controller may then retrieve the data in the cache areas when all of the data to be sent to the host in response to the host command is being cached.

Abstract: A first port of a device is connected to a first switch port of a first virtual switch defined within a switch device and a second port of the device is connected to a second switch port of a second virtual switch defined within the switch device. A target world wide port name of a target port of a storage system connected to the second virtual switch is identified by the device. The first port of the device is registered, in a first registration procedure, with the first virtual switch based on the target world wide port name. Registration information relating to an initiator port of a server that is associated with the target port is received in a second registration procedure. An initiator world wide port name of the initiator port of the server is determined based on the registration information. A storage volume in the storage system that is associated with the initiator port is identified based on the initiator world wide port name of the initiator port.

Abstract: Methods, systems, and computer readable media can be operable to facilitate the transfer of content between two or more storage units. The transfer of content between two or more storage units can be based upon a count of the number of hits to a storage unit entry associated with the content. In embodiments, the transfer of content between two or more storage units can be further based upon a predetermined threshold associated with a period.