Abstract: A system and associated methods are disclosed for allocating memory in a system providing translation of virtual memory addresses to physical memory addresses in a parallel computing system using memory striping. One method comprises: receiving a request for memory allocation, identifying an available virtually-contiguous physically-non-contiguous memory region (VCPNCMR) of at least the requested size, where the VCPNCMR is arranged such that physical memory addresses for the VCPNCMR may be derived from a corresponding virtual memory addresses by shifting a contiguous set of bits of the virtual memory address in accordance with information in a matching row of a virtual memory address matching table, and combining the shifted bits with high-order physical memory address bits also associated with the determined matching row and with low-order bits of the virtual memory address, and providing to the requesting process a starting address of the identified VCPNCMR.

Abstract: Aspects of the invention are provided to support partial file caching on a file system block boundary. All read requests are converted so that offset and count are aligned on a block boundary. Data associated with read requests is first satisfied from local cache, with cache misses supported with a call to persistent or remote system. Similarly, for a write request, any partial blocks are aligned to the block boundary. Data associated with the write request is performed on local cache and placed in a queue for replay to the persistent or remote system.

Abstract: A processor system according to the present invention includes a storage unit, a control information area that stores an access prohibit flag capable of switching from an allow side to a prohibit side, a main PEa that issues an access request to the storage unit and a request for rewriting a copy register, a security PE that evaluates whether or not the request for rewriting the copy register is valid, the copy register that stores, when the access prohibit flag is set to the allow side, a value corresponding to the allowance and, when the access prohibit flag is set to the prohibit side, a value corresponding to an evaluation result by the security PE, and an access control circuit that controls whether or not to allow access from the main PEa to the storage unit based on an output value from the copy register.

Abstract: A communication method applied to a transmission port between an access device and a control device includes: encoding a specific command to generate mode data; generating output data according to content of the mode data and content of command data corresponding to the specific command; and transmitting the output data from one of the access device and control device to the other via the transmission port. The other device of the access device and control device is used for receiving the output data and decoding the mode data of the output data to generate a decoding result, and selecting the specific command from a plurality of operational commands for executing a communication function corresponding to the specific command according to the decoding result.

Abstract: Audio data processing method and an audio data processing system are described. The audio data processing system includes an audio collect module, a processing module, a virtual play module, a virtual collect module, and a buffer memory. The virtual play module and the virtual collect module are registered in an application interface layer of a third-part software. The third-part software chooses the virtual play module and the virtual collect module. The virtual play module is configured for receiving audio data processed by the processing module and storing the processed audio data in the buffer memory. The virtual collect module is configured for collecting the processed audio data from the buffer memory and transmitting the processed audio data to the third-part software. The invention provides a universal solution suitable for any chatting tool by installing the virtual speaker and the virtual microphone.

Abstract: For dynamic memory relocation, a tracking module tracks accesses to a plurality of memory devices. Each of the plurality of memory devices is in communication with one memory controller of a plurality of memory controllers embedded in a computing device comprising a plurality of nodes. A migration module migrates first data from a first memory device in communication with a first memory controller to a second memory device in communication with a second memory controller.

Abstract: A synchronization method is provided for a peripheral apparatus. The peripheral apparatus comprises a first peripheral device and a second peripheral device, wherein the first peripheral device is coupled to a host and the first peripheral device runs in a first operation mode. The synchronization method comprises the following steps: when a second peripheral device is coupled to the host, the second peripheral device obtains a synchronization signal from the host; and the second peripheral device runs in a second operation mode based on the synchronization signal, wherein the second operation mode is same as the first operation mode.

Abstract: A method for externally configuring a device, wherein the device is devised for configuring, comprising positioning in a sufficient proximity external to the device a portable object provided with a representation of a configuration data for the device, wherein the representation is according to a standard non-custom industrial practice, further obtaining by the device the representation from the portable object, deciphering the representation into the configuration data by the device, and responsively configuring the device according to the configuration data by the device, and an apparatus for performing the same.

Abstract: For a plurality of input/output (I/O) operations waiting to assemble complete data tracks from data segments, a process, separate from a process responsible for the data assembly into the complete data tracks, is initiated for waking a predetermined number of the waiting I/O operations.

Abstract: A data processing device includes processing circuitry 20 for executing a first memory access instruction to a first address of a memory device 40 and a second memory access instruction to a second address of the memory device 40, the first address being different from the second address. The data processing device also includes prefetching circuitry 30 for prefetching data from the memory device 40 based on a stride length 70 and instruction analysis circuitry 50 for determining a difference between the first address and the second address. Stride refining circuitry 60 is also provided to refine the stride length based on factors of the stride length and factors of the difference calculated by the instruction analysis circuitry 50.

Abstract: A device comprises a central processing unit (CPU) and a memory configured for storing memory descriptors. The device also includes an analog-to-digital converter controller (ADC controller) configured for managing an analog-to-digital converter (ADC) using the memory descriptors. In addition, the device includes a direct memory access system (DMA system) configured for autonomously sequencing conversion operations performed by the ADC without CPU intervention by transferring the memory descriptors directly between the memory and the ADC controller for controlling the conversion operations performed by the ADC.

Abstract: A semiconductor device includes a memory block including memory cells coupled to bit lines, read/write circuits each including cache latch suitable for temporarily storing data to be stored in the memory cells, wherein the read/write circuits are divided into a plurality of groups and perform a program operation to store the data in the memory cells coupled to the bit lines, and an initialization control unit suitable for initializing the cache latches of the read/write circuits of a group corresponding to the address before the data is input to the cache latches, when a program command and an address are input.

Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.

Abstract: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.

Abstract: A method implemented by a non-volatile memory (NVM) controller comprising obtaining a NVM express (NVMe) command comprising a namespace identifier (NSID) from a host memory via a peripheral component interconnect express (PCIe) function, determining a mapping between the PCIe function and a namespace identified by the NSID based on a data structure stored in a PCIe memory address space, and accessing the namespace based on the mapping between the PCIe function and the namespace.

Abstract: An information processing apparatus including a plurality of nodes. The each of the nodes comprises a processor, a storage device, and a storing unit that stores therein multiple pointer sets in each of which a write pointer indicating an address used when data received from another node is stored in the storage device is associated with a read pointer indicating an address used when the data is read from the storage device. The each of the nodes comprises a notifying unit that notifies a node corresponding to a transmission source of the data of a pointer identifier that indicates a pointer set. The each of the nodes comprises a retaining unit that retains the received data in the storage device in accordance with an address indicated by a write pointer in a pointer set indicated by the pointer identifier.

Abstract: A system and method for data storage. The method can include: identifying, by a computer processor, a cluster map representing a set of storage resources; for each storage resource of the set of storage resources: traversing, by the computer processor, the cluster map to map the storage resource to a candidate resource set including at least one other storage resource of the set of storage resources; identifying a first data object associated with a storage request; identifying a first candidate resource set based on the first data object; and selecting a first final resource set based at least on the first candidate resource set, where the first data object is sent to storage resources of the first final resource set for storage.

Abstract: An information handling system includes a processor, a memory communicatively coupled to the processor, and an information storage device coupled to the processor via an input/output (I/O) bus for communicating I/O data between the processor and the information storage device. The device further receives a specification of reporting criteria for information storage device parameters.

Abstract: An expandable wireless storage device is provided that includes an interface slot, internal memory, a wireless interface and an aggregated file system view providing component. An external memory, which stores a first subset of multi-media files, can be physically coupled with the expandable wireless storage device using the interface slot. A second subset of multi-media files can be stored on the internal memory. A multi-media file of the multi-media files can be streamed to a playing device using the wireless interface. The internal memory is used as a buffer when the multi-media file resides on the external memory. An aggregated file system view providing component provides an aggregated file system view of the multi-media files.

Abstract: According to one embodiment, a first controller is connected to one of a plurality of terminals. A detector is configured to detect a connection between each of the plurality of terminals and an MHL cable. A power supply module supplies electric power to a first connected apparatus connected via a first MHL cable in response to a first connection detection between a first terminal and the first MHL cable. A second controller is configured to connect the first terminal and the first controller, in response to the first connection detection, and to connect a second terminal and the first controller, when a signal is not received from the first connected apparatus via the first terminal at a timing of a second connection detection between the second terminal and a second MHL cable.