Abstract: Disclosed is a memory management control system or the like, which can decrease degradation of processing performance. The memory management control system 1 includes an instruction unit 2. In the case that reference data referred to by a job, and first data existing in an area collected by a storage apparatus are identical, the instruction unit 2 issues a first instruction to write the first data in the storage apparatus, and in the case of not being identical, the instruction unit 2 does not issue the first instruction.

Abstract: Processors in a compute node offload transactional memory accesses addressing shared memory to a transactional memory agent. The transactional memory agent typically resides near the processors in a particular compute node. The transactional memory agent acts as a proxy for those processors. A first benefit of the invention includes decoupling the processor from the direct effects of remote system failures. Other benefits of the invention includes freeing the processor from having to be aware of transactional memory semantics, and allowing the processor to address a memory space larger than the processor's native hardware addressing capabilities. The invention also enables computer system transactional capabilities to scale well beyond the transactional capabilities of those found computer systems today.

Abstract: Multiple variants of a data processing system, which maintains I/O priority from the time a process makes an I/O request until the hardware services that request, will be described. In one embodiment, a data processing system has one or more processors having one or more processor cores, which execute an operating system and one or more applications of the data processing system. The data processing system also can have one or more non-volatile memory device coupled to the one or more processors to store data of the data processing system, and one or more non-volatile memory controller coupled to the one or more processors. The one or more non-volatile memory controller enables a transfer of data to at least one non-volatile memory device, and the priority level assigned by the operating system is maintained throughout the logical data path of the data processing system.

Abstract: The present disclosure relates to an apparatus and method capable of carrying out data movement in a memory of a terminal. The apparatus includes a processor configured to transmit a command for data movement and address information for data movement in a memory to the memory, and the memory configured to perform the data movement in units of word line in the memory by using the address information, in response to reception of the command for moving the data.

Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.

Abstract: A method for sharing peripheral devices in dual operating systems for an electronic device having at least one peripheral device is provided. The method includes: receiving a setting value for the peripheral device under the first operating system from a user; activating a second operating system; transmitting the setting value to the second operating system; and switching from the first operating system to the second operating system, wherein the second operating system sets the peripheral device with the setting value and enables the electronic device to operate under the second operating system.

Abstract: Devices, systems, and methods are described for allowing rules that are applied to one device to be applied to another device based on a user's interaction with only the devices. A rule-copy action, such as simultaneous shaking of the two devices, proximity of the two devices to each other, and/or the relative positions of the two devices, may be detected at one of the devices (e.g., a first device to which the user desires the rules or a copy of the rules to apply). In response to the rule-copy action, another device (e.g., a second device configured to operate according to the at least one rule) may be identified. The at least one rule may then be caused to be applied to the first device in response to detection of the rule-copy action, so as to configure the first device to operate according to the at least one rule.

Abstract: A network system enables monitoring the status of peripheral devices from computers without concentrating a load on the network. A specific device driver that runs on a specific computer connected to the network has an initialization command transmission unit that sends a first initialization command to the specific printer when a process command is sent to a specific printer, and an operating status monitoring unit that, after initialization based on the first initialization command is completed, monitors the operating status of the specific printer until the printer power turns off. Because the specific computer does not initialize and does not monitor the operating status of the specific printer until the computer sends a process command, concentrating a load on the network is avoided when the network system starts up.

Abstract: A hierarchical cache structure includes at least one real indexed higher level cache with a directory and a unified cache array for data and instructions, and at least two lower level caches, each split in an instruction cache and a data cache. An instruction cache of a split real indexed second level cache includes a directory and a corresponding cache array connected to the real indexed third level cache. A data cache of the split second level cache includes a directory connected to the third level cache. An instruction cache of a split virtually indexed first level cache is connected to the second level instruction cache. A cache array of a data cache of the first level cache is connected to the cache array of the second level instruction cache and to the cache array of the third level cache. A directory of the first level data cache is connected to the second level instruction cache directory and to the third level cache directory.

Abstract: According to an embodiment of the invention, a memory device includes an interface unit, a determining unit, a second command generating unit, and a processor. The interface unit receives a first command from the outside of the memory device. The determining unit determines whether the first command received by the interface unit is an access command that is a write command or a read command. When the determining unit determines that the first command is the access command, the second command generating unit extracts access destination information, which is address information or size information of an access destination, from the first command and generates a second command which includes the extracted access destination information and has a size less than that of the first command. The processor executes the second command.

Abstract: A storage controller system may include a host controller that queues host commands as data transfer commands in a plurality of queue channels. The storage controller system may also include a data storage controller that selects data transfer commands for execution. The data storage controller may select all data transfer commands associated with a host command when all of the data transfer commands are located at heads of the queue channels. Alternatively, the data storage controller may select for execution data transfer commands at heads of the queue channels when associated cache areas are available to receive data, regardless of whether all of the data transfer commands associated with a host command are at the heads. The host controller may then retrieve the data in the cache areas when all of the data to be sent to the host in response to the host command is being cached.

Abstract: Disclosed herein are several methods and systems for handling atomic write commands that reach scattered address ranges. One embodiment includes a method of performing an operation in a data storage device, the method comprising: receiving an atomic write command; obtaining a plurality of ranges of logical addresses affected by the atomic write command; for each of the plurality of affected ranges, assigning metadata information to track completion of a write operation performed at that range; performing the write operations in the ranges of logical addresses; updating the metadata information upon completion of the write operations in the ranges; and deferring an update to a translation map of the data storage device until the metadata information has been updated.

Abstract: A semiconductor memory device includes a plurality of memory strings each of which includes a series of memory cells that each store data having n bits (n?3), word lines, each connected in common to memory cells of different memory strings, and a control circuit which controls a first write operation and a second write operation. The first write operation includes a first step where a middle threshold voltage distribution is formed in memory cells and a second step following the first step where threshold voltages of some of the memory cells are increased, and the second write operation includes a step where threshold voltage distributions which correspond to the data having n bits is formed in the memory cells, wherein a write verify operation is performed after the first step but not after the second step of the first write operation.

Abstract: The embodiments provide a way to predict when a storage device will be accessed. In order to enhance performance, the storage device may proactively prepare for the access operation, and thus, minimize the access-time response of the storage device. The user behavior is recorded over time and collected into a dataset. In one embodiment, the intervals between the data points in the dataset are calculated and arranged into a matrix. Patterns in the matrix are recognized and used to recognize the next likely access by the user. The storage device may then take various actions, such as drive spin up, in anticipation of the next predicted access to minimize access-time response.

Abstract: Using a set of non-volatile storage media and a virtual input/output system operating in a memory sharing environment, by: (i) estimating which non-volatile storage medium, of the set of non-volatile storage media, will have the fastest access at a given time; and (ii) read-writing (that is, reading and/or writing) data by the virtual input/output system of a high importance page to the non-volatile storage media estimated to have the fastest access time.

Abstract: Methods, systems and computer program products are described for transferring aggregated data packets over an I/O interface from a host to a multiport embedded device. For example, a method includes receiving, by the device from the host, a single write command that (i) specifies two or more ports from among multiple ports of the device, and (ii) includes two or more data packets to be respectively written to the specified ports. The multiple ports of the device are mapped to corresponding locations of memory of the device. The method further includes saving, by the device in response to the single write command, the two or more data packets at two or more memory locations to which the specified ports are mapped. Additionally, the method includes sending, upon saving the data packets, a single notification to the host indicating that the device is ready to receive another write command.

Abstract: Using a set of non-volatile storage media and a virtual input/output system operating in a memory sharing environment, by: (i) estimating which non-volatile storage medium, of the set of non-volatile storage media, will have the fastest access at a given time; and (ii) read-writing (that is, reading and/or writing) data by the virtual input/output system of a high importance page to the non-volatile storage media estimated to have the fastest access time.

Abstract: A semiconductor memory device includes a cell array including a plurality of cell regions, a row decoder configured to drive rows corresponding to cell regions in which a refresh operation is to be performed, based on a counting address, and a refresh address generator configured to generate the counting address and a modified address in response to a control signal, wherein the modified address is generated by inverting at least one bit of the counting address, and wherein the semiconductor memory device performs concurrent refresh operations on a first cell region corresponding to the counting address and a second cell region corresponding to the modified address where the second cell region is determined to have weak cells.

Abstract: Provided is a method of delivering a user input received from a Human Interface Device (HID) to a source device by a sink device. The method includes: receiving the user input from the HID; generating HID user input information including a first field that represents a type of the HID, a second field that represents an interface type of the HID, and a third field that includes the user input received from the HID; and transmitting the configured HID user input information to the source device.

Abstract: Systems and methods for reducing metadata in a write-anywhere storage system are disclosed herein. The system includes a plurality of clients coupled with a plurality of storage nodes, each storage node having a plurality of primary storage devices coupled thereto. A memory management unit including cache memory is included in the client. The memory management unit serves as a cache for data produced by the clients before the data is stored in the primary storage. The cache includes an extent cache, an extent index, a commit cache and a commit index. The movement of data and metadata is by an interval tree. Methods for reducing data in the interval tree increase data storage and data retrieval performance of the system.