Abstract: A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.

Abstract: A semiconductor device may be formed with a floating body positioned over an insulator in a semiconductor structure. A gate may be formed over the floating body but spaced therefrom. The semiconductor structure may include doped regions surrounding the floating body. The floating body provides a distributed capacitance and resistance along its length to form an integrated RC circuit. The extent of the resistance is a function of the cross-sectional area of the floating body along the source and drain regions and its capacitance is a function of the spacing between the doped regions and the body and between the gate and the body. In some embodiments of the present invention, compensation for input voltage variations may be achieved.

Abstract: A method for singulating a semiconductor silicon wafer (10) comprising a plurality of semiconductor dice (20) arranged along a multiplicity of intersecting streets (30). Initially, a layer of photoresist (15)is patterned on the backside of the wafer (10). The semiconductor silicon wafer (10) is then etched using dry etching methods. As such, slots (22) are etched through the silicon of the wafer (10) aligned to the streets (30) forming a perforation. Simultaneously, tethers (40) are formed between the slots (22) interconnecting the adjacent dice (20) in order to maintain the wafer (10) mechanically intact. Furthermore, a membrane comprising integrated circuitry on the silicon wafer (10) is formed. The dice (20) of the wafer (10) are then separated for various purposes along the perforations. This is accomplished by applying pressure, such as manual pressure, to the wafer (10) so as to sever the tethers (40) which interconnect the dice (20) at their region (50) of reduced dimension.

Abstract: A method of forming a CMOS structure, the method including the acts of: forming a gate structure over a substrate layer; forming a silicide layer over the substrate layer; forming shallow source/drain areas in the substrate layer; forming an oxide diffusion barrier layer over the structure; forming a metal absorption layer over the oxide diffusion barrier layer; and melting portions of the substrate layer directly overlying the shallow source/drain areas, thereby transforming the shallow source/drain areas into shallow source/drain regions. The act of melting includes the act of exposing the metal absorption layer to pulsed laser beams.

Abstract: Disclosed is a copper film selective formation method capable of reducing the material cost by selectively depositing copper in a necessary region of an undercoat film made of an arbitrary material such as a metal or an insulating material. This copper film selective formation method includes the steps of forming a thin film of a silane coupling agent or a surfactant on an undercoat film on a substrate, making a prospective copper film region of the thin film hydrophilic, and selectively forming a copper film in the hydrophilic prospective copper film region of the undercoat film by CVD of copper.

Abstract: A semiconductor contact structure for a merged dynamic random access memory and a logic circuit (MDL) and a method of manufacturing the contact structure to: (i) a cell contact pad; (ii) at least one active region; and (iii) at least one gate electrode simulaneously, whereby an electric short between the gate electrodes and the cell contact pad is avoided, even in the event a lithographic misalignment occurs and whereby it is possible to obtain an overlap margin in the cell region, even with an improved metal contact to the gate electrode in the peripheral circuit region of the semiconductor device.

Abstract: The present invention is related to a method for depositing a metal-containing film from a metal plating bath, comprising the steps of subsequently depositing a metal-containing layer from a metal plating bath followed by a heating step and/or a vacuum step, said subsequent steps being repeated for a number of times in different sequences.

Abstract: A surface micro-machined sensor uses a pedestal in a cavity to support a flexible structure and reduce the span of the flexible structure. The reduced span per sense area allows larger sensor areas without permitting forces to permanently deform the flexible structure or cause the structure to touch an opposite wall of the cavity. The flexible structure bonded to the pedestal and an elevated region surrounding the pedestal defines a cavity between the flexible membrane and a lower plane region. Active regions can be formed in the lower plane region for capacitors or transistors. A pedestal can be of various shapes including a circular, ovoid, rectangular or polygonal shape. The lower plane region can be of various shapes including a ring or donut shape, ovoid, rectangular or polygonal shape with an inner dimension corresponding to the outer dimension of the pedestal. The elevated region can be of various shapes with an inner dimension corresponding to the outer dimension of the lower plane region.

Abstract: A method of manufacturing a semiconductor device, in which the depth of a divot in a shallow trench isolation can be decreased. The method comprises forming a trench in a semiconductor substrate, for isolating elements, forming a nitride film on a surface of the trench, depositing mask material on an entire surface of the semiconductor substrate, filling the trench with the mask material, etching the mask material until a surface level of the mask material in the trench falls below the surface of the semiconductor substrate, removing an exposed upper portion of the nitride film on the surface of the trench, removing the mask material from the trench, filling the trench with element-isolating material, thereby forming an element-isolating region, and forming a transistor in an element region isolated from another element region by the element-isolating region.

Abstract: A method for forming high quality multiple thickness oxide layers having different thicknesses by eliminating descum induced defects. The method includes forming an oxide layer, masking the oxide layer with a photoresist layer, and developing the photoresist layer to expose at least one region of the oxide layer. The substrate is then heated and descummed to remove any residue resulting from developing the photoresist. Alternatively, the photoresist layer may be cured prior to heating and descumming the substrate. The oxide layer is then etched, and the remaining photoresist is stripped before another layer of oxide is grown on the substrate.

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to annealing of the implants for dopant diffusion/activation and lattice damage relaxation. Lightly- or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.

Abstract: A manufacture method for a semiconductor device includes the steps of: (a) transporting a silicon wafer into a reaction chamber having first and second gas introducing inlet ports; (b) introducing an oxidizing atmosphere via the first gas introducing inlet port and raising the temperature of the silicon wafer to an oxidation temperature; (c) introducing a wet oxidizing atmosphere to form a thermal oxide film on the surface of the silicon wafer; (d) purging gas in the reaction chamber by using inert gas to lower a residual water concentration to about 1000 ppm or lower; and (e) introducing an NO or N2O containing atmosphere into the reaction chamber via the second gas introducing inlet port while the silicon wafer is maintained above 700° C. and above the oxidation temperature, to introduce nitrogen into the thermal oxide film and form an oxynitride film. A thin oxynitride film can be manufactured with good mass productivity.

Abstract: A microstructure comprises a conductive layer of aluminum, copper or alloys thereof on a substrate wherein the layer comprises metal grains at least about 0.1 microns and barrier material deposited in the grainboundaries of the surface of the metal is provided along with a method for its fabrication.

Abstract: A semiconductor chip package and a method of fabricating a semiconductor chip package provide a reduced chip size package. The semiconductor chip package includes a semiconductor chip; a plurality of pads disposed on an upper surface of the semiconductor chip; a thermosetting resin formed on the upper surface of the semiconductor chip such that through-holes in the thermosetting resin expose the pads; a multi-layer wiring pattern formed on the thermosetting resin; a connecting unit electrically connecting the multi-layer wiring pattern with the pads; a solder resist on the thermosetting resin and at least on of the multi-layer wiring pattern and the connecting unit, such that at least one through-hole in the solder resist exposes a portion of at least one of the multi-layer wiring pattern and the connecting unit; and a solder ball mounted on the through-hole of the solder resist in contact with the exposed portion of the at least one of the multi-wiring pattern and the connecting unit.

Abstract: A combined preanneal/oxidation step using a rapid thermal process (RTP) for treatment of a silicon wafer to form a thermal oxide of a given thickness while simultaneously adjusting the denuded zone depth and bulk micro defect density (BMD) comprising: exposing the wafer to a controlled temperature and a controlled preannealing time in an oxidation ambient at ambient pressure to obtain a target thermal oxide thickness that is preselected to correspond to a preselected denuded zone depth.

Abstract: A merged two transistor memory cell of an EEPROM, and method of fabricating same, is provided. The memory cell includes a substrate and insulating layer formed on the substrate. It also includes a memory transistor having a floating gate and a control gate, and a select transistor having a gate that is shared with the memory transistor. The memory cell is configured so that the shared gate serves both as the control gate of the memory transistor and the wordline of the select transistor. The memory cell further includes an ONO stack film that is disposed between the floating gate and the shared gate. In fabricating the memory, the ONO stack film is formed adjacent to the top and side surfaces of the floating gate. The ONO stack film is also formed so as not to be interposed between a potion of the shared gate that is adjacent to the substrate and the insulating layer.

Abstract: A method of making a circuitized substrate for use in an electronic package wherein the substrate, e.g., ceramic, includes more than one conductive layer, e.g., copper, thereon separated by a suitable dielectric material, e.g., polyimide. Each layer includes its own conductive location(s) which are designed for being directly electrically connected, e.g. using solder, to respective contact sites on a semiconductor chip to form part of the final package. Significantly, the resulting package does not include interconnections between the conductive layers at the desired contact locations; these locations, as mentioned, instead being directly connected to the chip.

Abstract: A method for evaluating the concentration of impurities in gases and equipment used in heat treatment of a semiconductor substrate is provided. The method includes processing a semiconductor substrate of known impurity levels in a heat treatment furnace, and measuring the impurity levels after the heat treatment processing by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of the substrate to getter impurities from the substrate into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were transferred to the substrate from the heat treatment process.

Abstract: Provided are a self-aligned semiconductor fuse structure, a method of making such a fuse structure, and apparatuses incorporating such a fuse structure. The fuse break point, that point at which the electrical link of which the fuse is part is severed by a laser beam, is self-aligned by the use of photolithographically patterned anti-reflective dielectric coatings. The self-alignment allows the size location of the break point to be less sensitive to the laser beam size and alignment. This has several advantages including allowing photolithographic control and effective size reduction of the laser spot irradiating the fuse material and surrounding structure. This permits reduced fuse pitch, increasing density and the efficiency of use of chip area, and results in reduced thermal exposure, which causes less damage to chip. In addition, laser alignment is less critical and therefore less timely, which increases throughput in fabrication.

Abstract: A method for separating a semiconductor wafer into several thousand devices or dies by laser ablation. Semiconductor wafers are initially pre-processed to create multiple devices, such as blue LEDs, on the wafers. The wafers are then mounted with tape coated with a generally high level adhesive. The mounted wafer is then placed on a vacuum chuck (which is itself positioned on a computer controlled positioning table) to hold it in place during the cutting process. The cutting surface is then covered with a protective layer to prevent contamination from the effluent resulting from the actual cutting process. A laser beam is generated and passed through optical elements and masks to create a pattern, such as a line or multiple lines. The patterned laser projection is directed at the wafer at a substantially normal angle and applied to the wafer until at least a partial cut is achieved through it.