Abstract: A method for evaluating the concentration of impurities in as-grown monocrystalline semiconductor ingots is provided. The method includes growing a monocrystalline semiconductor ingot, and measuring the bulk impurity levels of the ingot by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of a sample of the monocrystalline semiconductor ingot to getter impurities from the sample into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were grown into the monocrystalline semiconductor ingot.

Abstract: A method for evaluating the concentration of impurities in a semiconductor substrate. The method includes drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of the substrate to getter impurities from the substrate to the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were in the substrate prior to the drawing together.

Abstract: The specification describes a process for forming a barrier layer on copper metallization in semiconductor integrated circuits. The barrier layer is effective for both wire bond and solder bump interconnections. The barrier layer is Ti/Ni formed on the copper. Aluminum bond pads are formed on the barrier layer for wire bond interconnections and copper bond pads are formed on the barrier layer for solder bump interconnections.

Abstract: A semiconductor device having a contact structure that can exhibit superlative step coverage without causing voids or wiring discontinuities, using aluminum or aluminum alloys as a conductive substance for via-holes. A method of fabricating the semiconductor device comprises, for at least one layer of wiring regions above the first wiring region on a semiconductor substrate, the following steps (a) to (f): (a) a step of forming a via-hole in a second interlayer dielectric formed above the first wiring region on a semiconductor substrate; (b) a degassing step for removing gaseous components included within the interlayer dielectric by a heat treatment under reduced pressure and at the substrate temperature of 300° C. to 550° C.; (c) a step of forming a wetting layer on the surface of the interlayer dielectric and the via-hole; (d) a step of cooling the substrate to a temperature of no more than 100° C.

Abstract: The present invention is a method and apparatus for a very low profile ball grid array package. A substrate is provided with an aperture. A thin sheet material is secured to the substrate, covering the aperture, so as to form a cavity. A semiconductor die is mounted in the formed cavity on the thin sheet material. The semiconductor die is encapsulated with the thin sheet material supporting it during encapsulation. The use of the thin sheet material to form the cavity is a cost effective way to construct a ball grid array package having a very low profile.

Abstract: A method for forming a Cu interconnect pattern on a ZnO film of a printed circuit board without using a metallic catalyst on the ZnO film includes the steps of replacing Zn in the ZnO film by Cu in an aqueous solution of copper sulfate to form a CuO film, reducing the CuO in the CuO film to Cu in an aqueous solution of hydrogenated boron potassium to form a metallic Cu film, and plating the metallic Cu film with a plating Cu film in a plating liquid. The absence of the metallic catalyst improves the insulation resistance of the Cu interconnect pattern in the printed circuit board.

Abstract: To cause a crack at a fixed position in a separation layer, a method of separating a composite member includes the steps of forming a separation layer inside a composite member, forming inside the separation layer a stress riser layer in which an in-plane stress has concentratedly been produced to an extent that does not cause separation by the in-plane stress, and enlarging the in-plane stress to cause a crack in the stress riser layer, thereby separating the composite member.

Abstract: A method for implementing a self-aligned metal silicide gate is achieved by confining a metal within a recess overlying a channel and annealing to cause metal and its overlying silicon to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The metal is removed except for the portion of the metal in the recess. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.

Abstract: There is disclosed a method of manufacturing a semiconductor device, wherein a thin film containing a metal and capable of bonding with oxygen is deposited on a silicon substrate, a metal oxide film is formed on the thin film, and the thin film is oxidized by heat treatment to form a gate insulating film comprising the oxidized thin film and the metal oxide film.

Abstract: Methods of forming a metal interconnects include forming an electrically insulating layer having a contact hole therein, on a substrate. A step is also performed to form an electrically conductive seed layer. The seed layer extends on a sidewall of the contact hole and on a portion of an upper surface of the electrically insulating layer extending adjacent the contact hole. The seed layer is sufficiently thick along an upper portion of the sidewall and sufficiently thin along a lower portion of the sidewall that an upper portion of the contact hole is partially constricted by the seed layer and a constricted contact hole is thereby defined. An anti-nucleation layer is deposited on a portion of the seed layer that extends outside the constricted contact hole. The constricted contact hole is used as a mask to inhibit deposition of the anti-nucleation layer adjacent a bottom of the constricted contact hole.

Abstract: A method of fabricating a buried channel FET including providing a relaxed SiGe layer on a substrate, providing a channel layer on the relaxed SiGe layer, providing a SiGe cap layer on the channel layer, and ion implanting a dopant supply. The dopant supply can be ion implanted in either the SiGe cap layer or the relaxed SiGe layer. In another embodiment, there is provided a method of fabricating a circuit including providing at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET on a substrate, and ion implanting a dopant supply in the depletion mode FET.

Abstract: Degradation of fluorine-doped silica glass low-k inter-layer dielectrics during fabrication is significantly reduced and resolution of submicron features is improved by the formation of dual nature capping/ARC layers on inter-layer dielectric films. The capping/ARC layer is formed in-situ on a fluorine-doped silica glass inter-layer dielectric. The in-situ formation of the capping/ARC layer provides a strongly adhered capping/ARC layer, formed with fewer processing steps than conventional capping and ARC layers.

Abstract: A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of forming the metal-silicide layer on the surface of the impurity-diffused region between the steps of implanting impurities to form an impurity-implanted region and annealing for reactions of cobalt and silicon of the diffused layer. The above-mentioned method of forming the metal-silicide layer on the surface of the impurity-diffused region proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.

Abstract: A thin film transistor. The thin film transistor comprises a substrate, a dielectric layer and a polysilicon layer. A gate electrode is located on the substrate. A dielectric layer is located on the substrate and the gate electrode. A polysilicon layer is located on the dielectric layer. The polysilicon layer comprises a channel region and a doped region, wherein the channel region is located above the gate electrode and the doped region is adjacent to the channel region.

Abstract: The present invention silicon germanium bipolar device is fabricated by growing a silicon germanium layer on a semiconductor substrate followed by depositing a first oxide layer, a first polysilicon layer, and a first nitride layer on the silicon germanium layer. A well is etched through the first nitride layer and first polysilicon layer, exposing the first oxide layer on the bottom of the well, and the first nitride layer and first polysilicon layer on the side walls of the well. To cover the exposed edges of the first nitride layer and first polysilicon layer along the walls of the well, a second nitride layer is deposited and etched, forming nitride spacers along the sides of the well. The first oxide layer at the bottom of the well area is etched, creating gaps between the silicon germanium and first polysilicon layer. A second polysilicon layer is deposited in the gaps, creating a contact region electrically connecting the first polysilicon layer to the silicon germanium layer.

Abstract: In a TFT using a crystalline semiconductor film of a bottom gate type, a gate insulating film is flattened. On a substrate, an underlying film, a gate wiring and a gate insulating film are accumulated in this order. The gate insulating film includes a flattening film including an insulating organic resin film, such as BCB, polyimide and acrylic, and an insulating inorganic film. Because the surface of the gate insulating film is flattened by the flattening film, a flat amorphous semiconductor film can be formed on the surface thereof. Therefore, in the laser crystallization, since no difference in focal point of the laser light is formed among each position of the semiconductor film, crystallization can be uniformly conducted. Because the edge part of the gate wiring can be covered with the thick flattening film, implantation of an electron or a hole to the gate insulating film, and electrostatic breakage of the gate insulating film can be prevented.

Abstract: A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of refractory-metal-silicification of diffused regions between the steps of implanting impurities to form an impurity-implanted region and annealing for refractory-metal-silicification of the diffused layer. The refractory-metal-silicification of the diffused regions proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.

Abstract: A chip photoelectric sensor assembly includes a substrate with a printed circuit board mounted thereon. A photoelectric sensor chip is provided with a plurality of photoelectric sensors and is mounted on the substrate such that the photoelectric sensor chip is electrically connected with the substrate. The photoelectric sensors of the photoelectric sensor chip are masked by a photosensitive protective layer made of a photosensitive hard coating material. The photosensitive protective layer has a thickness ranging between 1 and 10 microns. The very thin photosensitive protective layer is thus capable of minimizing the light refraction distortion.

Abstract: The present invention of “Packaging of Light-Emitting Diode” is mainly to use silicon wafer as the substrate, whose crystal surface has a specific orientation for etching to form grooves. On the back of silicon substrate, dry etching is used for through-hole electrodes. Meanwhile, the insulating oxide layer or the nitride layer on silicon surface is plated with a reflective layer and an electrode layer, so the LED substrate is actually made of “silicon substrate”. Through the procedures including placement of LED chips in the grooves of a silicon substrate, die bonding, wire bonding, encapsulation and cutting, SMD LED can be formed. Compared to traditional LED packaging that uses circuit boards or metal leadframes as main packaging substrates, the present invention is a breakthrough, which uses silicon wafers as substrates, so it has several advantages including good heat dissipation, high heat resistance and easy miniaturization, which are not seen in common LED presently.

Abstract: A method for fabricating a semiconductor structure includes growing regions of oxide on a first structure, to form bit-line regions; wherein said semiconductor structure includes a semiconducting substrate, a patterned ONO layer on said substrate, wherein said patterned ONO layer comprises regions of ONO and exposed regions of said semiconducting substrate, a patterned hard mask layer on said regions of ONO, and a patterned photoresist layer on said patterned hard mask layer.