Abstract: In the construction of electronic devices with one or more flip chips and, in some cases, one or more leadless components, mounted on a substrate, the interconnections are made with conductive adhesive deposited using specialized masks. A magnetic metal mask fabricated of a membrane of magnetic material is placed temporarily onto the face of a semiconductor wafer or of a circuit or other substrate. When properly positioned with respect to the wafer or substrate, such as by relational guide holes, the mask is held in place by the magnetic forces produced by a controllable electromagnet. Contact pad openings in the magnetic metal mask are formed by suitable means such as laser cutting or photo-etching. The magnetic metal mask may include a flexible interface layer on the side facing the wafer or substrate to assure tight sealing thereto, so as to reduce smearing and bridging of the conductive adhesive paste and avoid bridging between contact pads that might otherwise occur during deposition of the paste.

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs on an SOI substrate. The MOSFETs include elevated source and drain regions. The elevated source and drain regions are amorphized before doping. Neutral ion species can be utilized to amorphize the elevated source and drain region. Dopants are activated in a low-temperature rapid thermal anneal process.

Abstract: Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

Abstract: A method is proposed for forming solder areas over a lead frame through deposition of an oxidation layer rather than selective removal of a polyimide-made solder mask, which allows the fabrication of the lead frame to be carried out in a more cost-effective and advantageous manner. The method allows the fabrication of the lead frame to be carried out through stamping without etching. Moreover, it can make the overall integrated circuit package less easily subjected to cracking and more securely assembled. Still moreover, it can make the overall integrated circuit package less likely to be weakened in structural strength by moisture. This method is therefore more advantageous to use than the prior art.

Abstract: A method and system for verifying a correct orientation of a module during installation of the module into a circuit board mounting site. The module housing is symmetric in at least one respect such that the module may be positioned in at least one alternate orientation with respect to the mounting site in addition to the correct orientation. Within the module, a module test contact is electrically connected to a common plane mode contact. A mounting site test contact that engages the module test pin when the module is correctly aligned with respect to the mounting site is preselected to be tested upon placement of the module onto the mounting site. A test signal is applied to a conductive common plane within the mounting site to which a common plane mounting site contact is connected. Prior to installation of the module into the mounting site, the mounting site test contact is electrically isolated from the conductive common plane to which a test signal is applied.

Abstract: A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.

Abstract: A semiconductor device includes a first gate stack and a second gate stack, each gate stack corresponding to a gate of a FET formed on the semiconductor device. The first gate stack includes a gate material formed from one of poly-silicon, poly-SiGe, and amorphous silicon. The gate material is implanted with a dopant of a first conductivity type at a first concentration. A metal silicide layer is formed over the doped gate material. The second gate stack includes a gate material formed from one of poly-silicon, poly-Si—Ge, and amorphous silicon. The gate material of the second gate stack is implanted with a dopant of a second conductivity type at a second concentration.

Abstract: A method for forming an oxide of substantially uniform thickness on at least two crystallographic planes of silicon, in accordance with the present invention, includes providing a substrate where silicon surfaces have at least two different crystallographic orientations of the silicon crystal. Atomic oxygen (O) is formed for oxidizing the surfaces. An oxide is formed on the surfaces by reacting the atomic oxygen with the surfaces to simultaneously form a substantially uniform thickness of the oxide on the surfaces.

Abstract: A method is provided for promoting adhesion of CVD copper to diffusion barrier material in integrated circuit manufacturing. The method uses a two-step CVD copper metallization process. Following deposition of a diffusion barrier layer on the IC substrate, a first layer of CVD copper is deposited on the barrier material. The first layer is preferably thin (less than 300 Å) and deposited using a precursor which yields an adherent conforming layer of copper. The suggested precursor for use in depositing the first layer of CVD copper is (hfac)Cu(1,5-Dimethylcyclooctadiene). The first layer of CVD copper serves as a “seed” layer to which a subsequently-deposited “fill” or “bulk” layer of CVD copper will readily adhere. The second copper deposition step of the two-step process is the deposit of a second layer of copper by means of CVD using another precursor, different from (hfac)Cu(1,5-Dimethylcyclooctadiene).

Abstract: A method for fabricating a semiconductor device, in accordance with the present invention, includes the steps of providing a semiconductor wafer having exposed p-doped silicon regions and placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the exposed p-doped silicon regions to form an oxide on the exposed p-doped silicon regions when a potential difference is provided between the wafer and the solution.

Abstract: A package for semiconductor devices, comprising a core board having a front side with a front side base wiring pattern formed thereon and a back side with a back side base wiring pattern formed thereon, the front and back side wiring patterns being electrically connected to each other through a conductor segment penetrating the core board; a front side laminate of upper wiring patterns with intermediate insulating layers intervening therebetween on the front side base wiring pattern, in which each adjacent pair of the upper wiring patterns are electrically connected to each other through a via plated coating on a side wall of viaholes penetrating one of the intermediate insulating layers that intervenes between the adjacent pair and in which an outermost one of the upper wiring patterns is patterned for electrical connection to a semiconductor chip; a back side laminate of insulating layers on the back side base wiring pattern; an external connection wiring pattern including external connection terminals on t

Abstract: A method for manufacturing a chip scale package comprises preparing a tape wiring board that includes a polyimide tape having top and bottom surfaces, Cu traces formed on the bottom surface of the tape, a window formed in the tape to enable the Cu traces to be connected to a semiconductor chip attached below the board, multiple connection holes formed in the tape to expose portions of the Cu traces therethrough and define solder ball mounting pads, and an elastomer chip carrier attached to the bottom surface of the tape. The method includes applying either a pre-flux or a cover sheet over the solder ball mounting pads. The pre-flux and the cover sheet each prevents the solder ball mounting pads being plated with gold. This, in turn, prevents the formation of intermetallic compounds in the solder balls so that the bond strength between the solder balls and a pad to which they attach is improved.

Abstract: A semiconductor device with an improved speed response has a linear ridge pattern including an active layer, a cladding layer, a current blocking layer, and a contact layer on a semiconductor substrate. The insulating layer may be formed in a pattern having a high resistance to dry etching along a longitudinal side of the ridge pattern.

Abstract: A MOS transistor and a method of fabricating the same for Ultra Large Scale Integration applications includes a composite gate structure. The composite gate structure is comprised of a main gate electrode and two assisted-gate electrodes disposed adjacent to and on opposite sides of the main gate electrode via an oxide layer. Areas underneath the two assisted-gate electrodes form ultra-shallow “pseudo” source/drain extensions. As a result, these extensions have a more shallow depth so as to enhance immunity to short channel effects.