Abstract: A method for providing data channel virtualization between one or more devices and one or more applications is disclosed. In one example, a device policy manager (DPM) is initialized by creating an instance of the DPM before creating any application. Further, the DPM is configured for device management by identifying each device of the one or more devices and its associated device data channel (DDC) to be managed by the DPM. Each of the one or more devices is identified using an associated device identity (ID) and its corresponding DDC. Furthermore, one or more virtual data channels (VDCs) are created and provided to the one or more associated applications upon receiving a request from each of the one or more applications using a device identity (ID) and any application specific configuration parameters provided by the application.

Abstract: A non-volatile memory controller coordinates multiple datapath units along a datapath between a host side and a memory side by unit-to-unit communication, or by a datapath control unit that is in communication with multiple datapath units. Data of a data stream is prioritized so that it passes along the datapath without interruption.

Abstract: The present invention is a clustered storage system with which, even when access to the processor of another controller is sent from the processor of one controller, the processor of the second controller is able to prioritize processing of this access so that I/O processing is also prevented from being delayed. With the storage system of the present invention, the first processor of the first controller transmits request information which is to be processed by the second processor of the second controller to the second processor by differentiating between request information for which processing is to be prioritized by the second processor and request information for which processing is not to be prioritized, and the second processor acquires the request information by differentiating between request information for which processing is to be prioritized and request information for which processing is not to be prioritized.

Abstract: A system includes a processor with a front end to receive an instruction stream reordered by a software scheduler and including a plurality of memory operations and alias information indicating how a given memory operation may be evaluated. Furthermore, the processor includes a hardware scheduler to reorder, in hardware, the instruction stream for out-of-order execution. In addition, the processor includes a calculation module to determine, for a given memory operation and based upon the alias information, a checking range of memory atoms subsequent to the given memory operation and a virtual order of the memory operation. The virtual order indicates an original ordering of the instructions. The processor also includes an alias unit to reorder the instruction stream, determine whether the hardware reordering caused an error, and determine whether the software reordering caused an error based upon the checking range and the virtual order.

Abstract: A vector processor includes a plurality of execution units arranged in parallel, a register file, and a plurality of load units. The register file includes a plurality of registers coupled to the execution units. Each of the load units is configured to load, in a single transaction, a plurality of the registers with data retrieved from memory. The loaded registers corresponding to different execution units. Each of the load units is configured to distribute the data to the registers in accordance with an instruction selectable distribution. The instruction selectable distribution specifies one of plurality of distributions. Each of the distributions specifies a data sequence that differs from the sequence in which the data is stored in memory.

Abstract: A memory controller according to the embodiment includes a front-end unit that issues an invalidation command in response to a command from outside of the memory controller, the command including a logical address, an address translation unit that stores a correspondence relationship between the logical and a physical address, an invalidation command processing unit that, when the invalidation command is received, registers the logical address associated with the invalidation command as an invalidation registration region in an invalidation registration unit and issues a notification to the front-end unit, and an internal processing unit that dissolves a correspondence relationship between the logical address registered in the invalidation registration unit and the physical address in the address translation unit in a predetermined order by referencing the logical address registered in the invalidation registration unit.

Abstract: An improved technique involves performing computations for partial stripe updates in a RAID at individual disk controllers rather than at the RAID controller. When a RAID controller receives a request to update old payload data at a block in a particular disk with update data, it sends the update data to the controller of that particular disk. The disk controller reads internally old data from the block, computes the difference between new and old data, replaces the old data on disk with the new data, and returns the difference to the RAID controller. The RAID controller computes difference values of the parity data from the difference values of the payload data received from the disk controllers. It then sends these difference values to the controllers of disks storing parity data. A controller of a disk storing parity data reads internally the corresponding data block, adds to it the difference value, and writes the result back to disk.

Abstract: A semiconductor device and a memory system including the same are disclosed, which relate to a technology for reducing a toggle current of a global input output (GIO) of a semiconductor device configured to use a data bus inversion (DBI) scheme. The semiconductor device includes:a local input/output (LIO) line driver configured to perform inversion or non-inversion of data of a global input/output (GIO) line according to a control signal, and to output the inversion or non-inversion result to the LIO line; and an inversion processor configured to combine an inversion control signal and mat information, and output the control signal for controlling inversion or non-inversion of data to the LIO line driver.

Abstract: A bus driver circuit may include a first and a second circuit node, wherein the first circuit node is operably coupled to a bus line, which causes a bus capacitance between the first and the second circuit node. A switching circuit is coupled to the first circuit node and configured to apply an output voltage between the first and the second circuit node. Thereby the bus capacitance is charged when a control signal indicates a dominant state. A discharge circuit comprises at least one resistor. The discharge circuit is coupled between the first and the second circuit node and configured to allow the bus capacitance to discharge via the resistor when the control signal indicates a recessive state. The switching circuit is further configured to provide a temporary current path for discharging the bus capacitance during a transition period from a dominant to a recessive state.

Abstract: Techniques for managing a plurality of threads on a multi-threading processing core. Embodiments provide an instruction count threshold condition that determines how many countable instructions of a thread the multi-threading processing core will execute before context switching to another one of the plurality of threads. A first plurality of instructions for a first one of the plurality of threads is processed on the multi-threading processing core. Embodiments determine, for each of the first plurality of instructions, whether the instruction is a countable instruction, wherein at least one of the first plurality of instructions is not a countable instruction. A count of the countable instructions is maintained. Upon determining that the instruction count threshold condition is satisfied, based on the maintained count, embodiments context switch the multi-threading processing core to process a second plurality of instructions for a second one of the plurality of threads.

Abstract: Techniques for managing a plurality of threads on a multi-threading processing core. Embodiments provide an instruction count threshold condition that determines how many countable instructions of a thread the multi-threading processing core will execute before context switching to another one of the plurality of threads. A first plurality of instructions for a first one of the plurality of threads is processed on the multi-threading processing core. Embodiments determine, for each of the first plurality of instructions, whether the instruction is a countable instruction, wherein at least one of the first plurality of instructions is not a countable instruction. A count of the countable instructions is maintained. Upon determining that the instruction count threshold condition is satisfied, based on the maintained count, embodiments context switch the multi-threading processing core to process a second plurality of instructions for a second one of the plurality of threads.

Abstract: A memory device includes a memory cell array, a multi-purpose register (MPR) and a control unit. The memory cell array includes a plurality of memory blocks. The multi-purpose register (MPR) stores physical address information for each of the plurality of memory blocks. The control unit outputs the physical address information stored in the multi-purpose register in response to an MPR read command received from a memory controller.

Abstract: A floating-point unit and a method of identifying exception cases in a floating-point unit. In one embodiment, the floating-point unit includes: (1) a floating-point computation circuit having a normal path and an exception path and operable to execute an operation on an operand and (2) a decision circuit associated with the normal path and the exception path and configured to employ a flush-to-zero mode of the floating-point unit to determine which one of the normal path and the exception path is appropriate for carrying out the operation on the operand.

Abstract: A controller for controlling interrupt processing in a multiple-interrupt system is provided. The controller includes multiple watchdog timers (WDTs), each provided for each of interrupt priorities. The controller includes interrupt priority selectors, each of which receives each interrupt request signal and outputs an activation signal to a corresponding WDT according to the priority of the interrupt request signal. The controller includes an interrupt processing circuit, which when a WDT has timed out, outputs, to a processor, an interrupt request signal having a priority one or more levels higher than the priority corresponding to the WDT. When multiple causes of interrupt are assigned to one of the interrupt priorities, the interrupt processing circuit gives priority to an interrupt request signal caused by the timeout of a WDT lower in priority level than the interrupt priority to detect that an abnormal operation has occurred in interrupt processing having the lower level priority.

Abstract: A processor is described having a functional unit within an instruction execution pipeline. The functional unit having circuitry to determine whether substantive data from a larger source data size will fit within a smaller data size that the substantive data is to flow to.

Abstract: Adaptive data collection practices in a multi-processor device. The device may include a first processor and a second processor. The first processor may operate in any of a plurality of power states. The first processor may indicate to the second processor when it transitions to a different power state. The second processor may collect information relating to its operation. The second processor may collect the information according to different information collecting modes depending on in which power state the first processor is operating. Less information may be collected in an information collecting mode corresponding to a lower power state of the first processor than in an information collecting mode corresponding to a higher power state of the first processor.

Abstract: An instruction processing apparatus of an aspect includes a plurality of operation mask registers. The apparatus also includes a decode unit to receive an operation mask consolidation instruction. The operation mask consolidation instruction is to indicate a source operation mask register, of the plurality of operation mask registers, and a destination storage location. The source operation mask register is to include a source operation mask that is to include a plurality of masked elements that are to be disposed within a plurality of unmasked elements. An execution unit is coupled with the decode unit. The execution unit, in response to the operation mask consolidation instruction, is to store a consolidated operation mask in the destination storage location. The consolidated operation mask is to include the unmasked elements from the source operation mask consolidated together. Other apparatus, methods, systems, and instructions are also disclosed.

Abstract: Register renaming circuitry for a processing apparatus configured to process a stream of instructions from an instruction set specifying registers from an architectural set of registers. The apparatus including a physical set of registers configured to store data values being processed by the processing apparatus. Register renaming circuitry is configured to receive a stream of operations from an instruction decoder and to map registers that are to be written to by the stream of operations to physical registers within the physical set of registers that are currently available. The register renaming circuitry comprises register release circuitry configured to release the physical registers that have been mapped to the registers when a first set of conditions have been met, and to release the physical registers that have been mapped to the additional registers when a second set of conditions have been met.

Abstract: A processor executes a vector move instruction to move data elements from a second vector register to a first vector register under the control of a first mask register and a second mask register. A register file within the processor includes the first vector register, the second vector register, the first mask register and the second mask register. In response to the vector move instruction, execution circuitry in the processor is to replace a given number of target data elements in the first vector register with the given number of source data elements in the second vector register. Each source data element corresponds to a mask bit in the second mask register having a second bit value, and wherein each target data element corresponds to a mask bit in the first mask register having a first bit value.

Abstract: A method and apparatus of a device that captures a stackshot of an executing process is described. In an exemplary embodiment, the device detects an interrupt of the process occurring during the execution of the process, where the process execution can be in a kernel space and user space, and the interrupt occurs during the user space. The device further determines whether to capture a stackshot during the interrupt using a penalty function. If the stackshot is to be captured, the device captures the stackshot and saves the stackshot.