Abstract: The embodiments relate to dynamically allocating lanes of a computer bus. A computer system is configured with a plurality of connectors in communication with a module, with each connector configured to receive a respective adapter. The module detects a presence of each primary and backup adapter present, and controls an initial allocation of lanes to each detected primary adapter for maximizing adapter functionality. After the initial allocation and in response to detecting a failure of at least one primary adapter, the module dynamically switches lanes from the failed adapter to at least one of the one or more remaining primary adapters and the backup adapter.

Abstract: A device management apparatus includes circuitry configured to execute steps of determining whether a model of a setting subject in which a setting value accepted at first accepting is to be set is a model in which the setting value can be set; if it is determined that the model of the setting subject is a model in which the setting value cannot be set, acquiring a setting value associated with setting value identifying information similar to setting value identifying information input at the first accepting, from a first storage device configured to store a model, a setting value that can be set in the model, and a predetermined setting value identifying information about the setting value in association with one another; and transmitting the setting value acquired at the acquiring to a device of the model in which the setting value cannot be set.

Abstract: Including control data in a serial audio stream is presented herein. A device can include a clock component that is configured to send, via a clock pin of the device, a bit clock signal directed to a slave device. A frame component can send, via a frame pin of the device, a frame clock signal directed to the slave device. A control component can receive, via a data pin of the device during a first portion of a phase of a period of the frame clock signal, slave data from the slave device on a bit-by-bit basis based on the bit clock signal according to an integrated interchip sound (I2S) based protocol; and send, via the data pin during a second portion of the phase after the first portion, a set of control bits directed to the slave device on the bit-by-bit basis based on the bit clock signal.

Abstract: System, methods and apparatus are described that facilitate a device to encode/decode data in a data communications interface coupled to a plurality of wires. The device determines a value of a sequence of data bits allocated to a frame, converts the value into a sequence of symbols associated with the frame, and transmits the sequence of symbols to a receiver. The device performs the converting by calculating base-N coefficients of a base-N number polynomial for the frame based on the value, where N is greater than 2, calculating base-2 coefficients of a base-2 number polynomial for each symbol according to a respective base-N coefficient corresponding to each symbol, determining changes of states of the plurality of wires for each symbol according to the base-2 coefficients respectively calculated for each symbol, and generating the sequence of symbols based on the changes of states of the plurality of wires for each symbol.

Abstract: Methods and structure for devices that implement multiple versions of the Serial Attached Small Computer System Interface (SAS) protocol. One exemplary embodiment comprises a SAS device that includes at least one physical link (PHY) that supports a specified generation of SAS protocols, and at least one PHY that supports a different generation of SAS protocols and that does not support the specified generation of SAS protocols. The SAs device also includes an Input/Output (I/O) processor able to select a PHY to service a SAS connection, based on the generation of SAS protocols supported by the PHY.

Abstract: A communication apparatus comprising a plurality of signal processing units configured to perform a set of pre-determined signal processing functions according to a set of parameters, a plurality of programmable crossbars coupled to the plurality of signal processing units, and a plurality of control processors coupled to the plurality of programmable crossbars and configured to adjust the plurality of programmable crossbars to interconnect the signal processing units to implement a selected communication protocol, wherein at least one of the programmable crossbars routes data from a first of the plurality of signal processing units to a second of the plurality of signal processing units forming a data path without interception from the plurality of control processors.

Abstract: Low Latency Interconnect Integrated Event Handling has been disclosed. In one implementation a hardware based interrupt controller coupled with a hardware based event queue manager, dedicated hardware based queues, and processor instruction extensions allows for off-loading event processing from an operating system thereby dramatically lowering wasted processor cycles while speeding up event processing.

Abstract: Provided is a virtual interface, a “Forwarder” and a Virtual Block Storage Device (VBSD). The virtual interlace is the interface between a Command/Response Queue (CRQ), which receives CRQ commands from a hypervisor, and a common interface of the Forwarder. The Forwarder receives I/O commands in a format associated with the common interface and converts the commands into a generic I/O format. The reformatted command is transmitted to the VBSD. The hypervisor sends a read or write (R/W) request to the virtual interface, which passes the request to the Forwarder. The Forwarder receives the request, converts the request into a form readable by the VBSD and transmits the converted request to the VBSD. The VBSD transmits the request to a block storage device and returns the response to the Forwarder. The Forwarder replies to the request from the virtual interface with the response from the ABSD. The virtual interface then responds to the hypervisor.

Abstract: Processor context save latency is reduced by only restoring context registers with saved state that differs from the reset value of registers. A system agent monitors access to the design blocks and sets a dirty bit to indicate which design block has registers that have changed since the last context save. During a context save operation, the system agent bypasses design blocks that have not had context changes since the latest context save operation. During a context restore operation the system agent does not restore the context registers with saved context values that are equal to the reset value of the context register.

Abstract: Methods and apparatus are disclosed for fusing instructions to provide OR-test and AND-test functionality on multiple test sources. Some embodiments include fetching instructions, said instructions including a first instruction specifying a first operand destination, a second instruction specifying a second operand source, and a third instruction specifying a branch condition. A portion of the plurality of instructions are fused into a single micro-operation, the portion including both the first and second instructions if said first operand destination and said second operand source are the same, and said branch condition is dependent upon the second instruction. Some embodiments generate a novel test instruction dynamically by fusing one logical instruction with a prior-art test instruction. Other embodiments generate the novel test instruction through a just-in-time compiler.

Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.

Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.

Abstract: An interface device (10) provides fast data communication between a host device with input/output interfaces and a data transmit/receive device, wherein the interface device (10) comprises a processor means (13), a memory means (14), a first connecting device (12) for interfacing the host device with the interface device, and a second connecting device (15) for interfacing the interface device (10) with the data transmit/receive device. The interface device (10) is configured by the processor means (13) and the memory means (14) in such a way that, when receiving an inquiry from the host device via the first connecting device (12) as to the type of a device attached to the host device, regardless of the type of the data transmit/receive device, the interface device sends a signal to the host device via the first connecting device (12) which signals to the host device that it is communicating with an input/output device.

Abstract: Various embodiments are generally directed to instrumenting an interrupt service routine. A non-executable address may be provisioned and added to an execution stack to cause a page fault on a known address after execution of an interrupt service routine. The page fault on the known address can be used to trigger instrumentation operations and also to return to the interrupted process.

Abstract: A memory device and memory system using the memory device. The memory system includes a memory controller having a memory bus with a plurality of lanes, and a plurality of memory devices. Each memory device has a plurality of data pins and a plurality of detection circuits, wherein each detection circuit is coupled to one of the data pins to detect whether the data pin is coupled to one of the lanes of the memory bus. Each lane of the memory bus provides a point-to-point connection between the memory controller and exactly one of the device data lanes, wherein a subset of the data lanes of each memory device are coupled to one of the lanes of the memory bus. The memory capacity of a memory system may be increased by using more of the memory devices limited only by the width of the memory bus.

Abstract: Some die-stacked memories will contain a logic layer in addition to one or more layers of DRAM (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies. Additional circuitry/functionality is placed on the logic layer to implement functionality to perform various computation operations. This functionality would be desired where performing the operations locally near the memory devices would allow increased performance and/or power efficiency by avoiding transmission of data across the interface to the host processor.

Abstract: The present invention relates to a control circuitry module group, an electrical device, and a modem device. The control circuitry module group is configured for communication and/or power supply between a master control module and at least one slave modules in an electrical device. The control circuitry module group comprises: a bus; a bus control module coupled to the master control module and the bus, configured to receive a control signal from the master control module, add a target address in the control signal, and send to the bus the control signal with the target address; and at least one slave control modules each coupled to a corresponding slave module and the bus, respectively, and configured to receive the control signal with the target address via the bus, and controlling power supply to the slave module in response to the control signal.

Abstract: Systems and methods for write-behind caching in distributed file systems. An example method may comprise: receiving, over a network, a direct write request referencing data to be written to a file residing on a persistent data storage device, the file containing at least part of an image of a virtual machine disk; writing, by a processing device, the data to a cache entry of a memory-resident cache, the cache entry corresponding to at least a part of the file; acknowledging the write request as completed; and committing, asynchronously with respect to the acknowledging, the cache entry to the persistent data storage device.

Abstract: In one example embodiment of the inventive concepts, an adaptive data backup method performed in a memory system including a non-volatile multi-level cell memory device includes receiving a write command from a host and determining a backup data size which is a size of data to be backed up among data requested to be written in the write command. The adaptive data backup method further includes selecting a backup type among at least two different backup types, based on the backup data size and backing up the data according to the selected backup type.

Abstract: An electronic device may include system and serial peripheral interface (SPI) clocks, and a host interface each switchable between active and inactive states, a serial controller coupled to the system clock, and a memory. A slave controller may generate a request active signal based upon a transaction request from a host and causing each of the system clock, SPI clock, and host interface into the active state, store request data in the memory, and switch the host interface to the inactive state based upon the request data being stored. The serial controller may process the request based upon the request active signal, and generate a request complete signal based upon the request being processed. The slave controller may switch the system clock to the inactive state based upon the request complete signal. The SPI clock may be switched to the inactive state based upon the request complete signal.