Abstract: According to an embodiment, an information processing apparatus includes a plurality of cores, a shared resource that can be shared by the plurality of cores, and local registers that store configuration information peculiar to the respective cores. The shared resource is provided independently from the plurality of cores. The local registers are provided to the respective cores. This makes it possible to provide an information processing apparatus that can suppress increase in hardware resources even when the number of cores composing a multi-core system increases.

Abstract: By causing information processing apparatuses belonging to a same group to be in a same state and transmitting operation information received from an input unit to the information processing apparatuses belonging to the same group simultaneously or approximately simultaneously, the operations of the information processing apparatuses belonging to the same group are synchronized with each other, and operation results received from the synchronized information processing apparatuses belonging to the same group are output by an output unit. In this way, the plurality of grouped information processing apparatuses can be simultaneously operated.

Abstract: An electronic device includes a motherboard that includes a south bridge, a universal serial bus (USB) 3.0 connector, and a ground module. The south bridge is connected to the USB3.0 connector for transporting USB3.0 signals and USB2.0 signals. The grounded module is connected to the south bridge and the USB3.0 connector. The south bridge is used for controlling the ground module to work. The USB2.0 signals transmit between the south bridge and the USB3.0 connector flow into the ground, while the ground module is working.

Abstract: In one embodiment, a computer-implemented method includes instructing two or more processors that are operating in a normal state of a symmetric multiprocessing (SMP) network to transition from the normal state to a slow state. The two or more processors reduce their frequencies to respective target frequencies in a transitional state when transitioning from the normal state to the slow state. It is determined that the two or more processors have achieved their respective target frequencies for the slow state. The slow state is entered, responsive to this determination. Responsive to entering the slow state, a first processor of the two or more processors is instructed to send empty packets across an interconnect to compensate for a first greatest potential rate differential between the first processor and a remainder of the two or more processors during the slow state.

Abstract: A method for serial data transfer in a bus system having at least two bus subscribers that exchange messages via the bus, the transmitted messages having a logical structure according to CAN standard ISO 11898-1, the logical structure encompassing a start-of-frame bit, arbitration field, control field, data field, CRC field, acknowledge field, and end-of-frame sequence, the control field encompassing a data length code having an information item regarding the data field length. When a first marker (EDL) is present, the control field of the messages, divergently from the CAN standard ISO 11898-1, encompasses more than six bits; when the first marker (EDL) is present, the control field of the message is expanded to include at least one further bit (ESI); and the further bit (ESI) or one of the further bits causes an information item regarding the “error passive” state of the bus subscriber to be integrated into transmitted messages.

Abstract: Methods and systems may provide for an expansion card including one or more peripheral ports, a connection edge having a first bus interface and a second bus interface, and an input output (IO) controller coupled to the first bus interface and at least one of the one or more peripheral ports. The expansion card can also include an embedded controller coupled to the IO controller and the second bus interface, wherein the embedded controller has logic to receive a general purpose input output (GPIO) signal from the IO controller. The logic may also notify an off-card host device of the GPIO signal via the second bus interface. In one example, the IO controller is a Thunderbolt controller, the first bus is a PCI-e bus, and the second bus is an SMBus.

Abstract: In an embodiment, a router includes multiple input ports and output ports, where the router is of a source-synchronous hybrid network on chip (NoC) to enable communication between routers of the NoC based on transitions in control flow signals communicated between the routers. Other embodiments are described and claimed.

Abstract: A writing method, a memory controller and a memory storage device are provided. The writing method includes steps of: configuring logical addresses to map to part of physical programming units in a storage area, wherein at least one of the physical programming units stores a valid data; transmitting a first write command for writing data having a first data length to at least one of the physical programming units; receiving a status signal; and selecting a spare physical erasing unit and copying the valid data having a second data length to the spare physical erasing unit, after transmitting the first write command and before receiving the status signal, wherein the first data length is not greater than the second data length. Therefore, it prevents a host system from waiting too long when writing data.

Abstract: A reconfigurable register device includes an arrangement of storage elements arranged sequentially in a chain structure. Each storage element stores a state of a binary signal. A combinatorial logic circuitry connectable to the arrangement of storage elements enables the arrangement of storage elements to form a binary synchronous counter. A bypass logic circuitry connectable to the arrangement of storage elements enables the arrangement of storage elements to form a serial shift register. A switching circuitry has a mode signal input terminal receiving a mode signal indicative of at least one of a counter mode and a shift register mode. The switching circuitry is configured to connect the arrangement of storage elements to the combinatory logic circuitry if the mode signal indicates the counter mode, and to connect the arrangement of storage elements to the bypass logic circuitry if the mode signal indicates the shift register mode.

Abstract: Techniques for polling an input/output (I/O) device are described herein. The techniques include polling a device for data from the I/O device, and receiving the data from the I/O device at the host device as a result of the polling. The techniques include determining whether the data received is the same as data received at a previous polling of the I/O device. Upon determining the data received is the same, the techniques include decreasing the polling rate if the data is the same, and if it is not the same. Upon determining the data is not the same, the techniques include increasing the polling rate if the data is not the same.

Abstract: A processor includes a plurality of execution units. At least one of the execution units is configured to execute a complex instruction that requires multiple instruction cycles to execute, and to enforce atomic execution of the complex instruction during a first-portion of the multiple instruction cycles required to execute the complex instruction. The at least one of the execution units is further configured to enable execution of the complex instruction to be interrupted for execution of a different instruction by the at least one execution unit during execution of a second portion of the multiple instruction cycles. The first portion and the second portion are non-overlapping.

Abstract: A method of an aspect includes receiving a packed data operation mask concatenation instruction. The packed data operation mask concatenation instruction indicates a first source having a first packed data operation mask, indicates a second source having a second packed data operation mask, and indicates a destination. A result is stored in the destination in response to the packed data operation mask concatenation instruction. The result includes the first packed data operation mask concatenated with the second packed data operation mask. Other methods, apparatus, systems, and instructions are disclosed.

Abstract: Described herein are techniques for cancelling I/O requests. Initially, virtual memory of an application is assigned to a first portion of memory. The application may issue a read request to an external device. The external device is instructed to record any response to the read request in the first portion of memory. The read request may be cancelled as follows. The virtual memory of the application may be re-assigned to a second portion of the memory. If and when the external device finishes processing the read request, the external device's response to the read request may still be saved in the first portion of memory, even though the read request has been cancelled. Such action of the external device would ordinarily corrupt the virtual memory of the application, but due to the memory re-assignment, no corruption of the virtual memory occurs. Similar techniques may be applied to cancel write requests.

Abstract: Reconfiguring a register file using a rename table having a plurality of fields that indicate fracture information about a source register of an instruction for instructions which have narrow to wide dependencies.

Abstract: A vector reduction instruction is executed by a processor to provide efficient reduction operations on an array of data elements. The processor includes vector registers. Each vector register is divided into a plurality of lanes, and each lane stores the same number of data elements. The processor also includes execution circuitry that receives the vector reduction instruction to reduce the array of data elements stored in a source operand into a result in a destination operand using a reduction operator. Each of the source operand and the destination operand is one of the vector registers. Responsive to the vector reduction instruction, the execution circuitry applies the reduction operator to two of the data elements in each lane, and shifts one or more remaining data elements when there is at least one of the data elements remaining in each lane.

Abstract: An information handling system includes a processor configured to trap system management interrupts (SMIs) via a system management mode transfer monitor (STM), a first system resource, a SMI handler configured to operate within the STM, launch a first system management mode (SMM) virtual machine, load first SMM code for a first driver into the first SMM virtual machine, and associate the first SMM virtual machine with the first system resource and not with the second system resource.

Abstract: There is provided an information processing apparatus including a device detection part configured to detect a second execution device that is identical or similar to a first execution device which executes a command, and an execution control part configured to perform control in a manner that the command is executed by the second execution device detected by the device detection part.

Abstract: Embodiments are disclosed relating to methods of ordering transactions across a bus of a computing device. One embodiment of a method includes determining a current target memory channel for an incoming transaction request, and passing the incoming transaction request downstream if the current target memory channel matches an outstanding target memory channel indicated by a direction bit of a counter or the counter equals zero. The method further includes holding the incoming transaction request if the counter is greater than zero and the current target memory channel does not match the outstanding target memory channel.

Abstract: This application discusses, among other things, communication apparatus and methods, and more particularly, a single conductor or single wire communication scheme. In an example, a method for communicating between a master device and a slave device using a first single conductor can include transmitting a first ping on the first single conductor using a master device, the first single conductor configured to couple the master device to a slave device, receiving a slave ping on the first single conductor at the master device during a ping interval, toggling a logic level of the first single conductor prior to sending a first data packet using pulses having a duration of less than one half of a unit interval, such as a unit interval associated with a bit interval.

Abstract: A system, method, and computer program product are provided for remapping registers based on a change in execution mode. A sequence of instructions is received for execution by a processor and a change in an execution mode from a first execution mode to a second execution mode within the sequence of instructions is identified, where a first register mapping is associated with the first execution mode and a second register mapping is associated with the second execution mode. Data stored in a set of registers within a processor is reorganized based on the first register mapping and the second register mapping in response to the change in the execution mode.