Abstract: A processor may include a core to execute interrupt latency control unit (ILCU) software and an interrupt controller circuitry. The interrupt controller circuitry includes: a first register to store a first time value at which a first interrupt is received at the interrupt controller circuitry and a second register to store a second time value at which the first interrupt is delivered to the core. The ILCU software is to: read the first time value in the first register and the second time value in the second register; determine an amount of time the first interrupt was pending at the interrupt controller circuitry; determine interrupt configuration information that adjusts the first interrupt priority of a subsequent interrupt; and send the interrupt configuration information to the interrupt controller circuitry. The interrupt controller circuitry is to adjust the first interrupt priority of the subsequent interrupt to the second interrupt priority.

Abstract: SPI frame for simultaneously entering 8 bit daisy-chain mode from 16 bit register addressable mode. Some products that implement SPI may be connected in a daisy chain configuration, the first slave output being connected to the second slave input, etc. The SPI port of each slave is designed to send out during the second group of clock pulses an exact copy of the data it received during the first group of clock pulses. The whole chain acts as a communication shift register; daisy chaining is often done with shift registers to provide a bank of inputs or outputs through SPI. Large latency occurs during the entry into daisy-chain mode which increases as a function of the number of linked SPI devices. A means for simultaneously instructing all connected devices to enter/enable daisy-chain mode is disclosed.

Abstract: Provided is a virtual interface, a “Forwarder” and a Virtual Block Storage Device (VBSD). The virtual interface is the interface between a Command/Response Queue (CRQ), which receives CRQ commands from a virtual machine monitor, and a common interface of the Forwarder. The Forwarder receives I/O commands in a format associated with the common interface and converts the commands into a generic I/O format. The reformatted command is transmitted to the VBSD. The virtual machine monitor sends a read or write (R/W) request to the virtual interface, which passes the request to the Forwarder. The Forwarder receives the request, converts the request into a form readable by the VBSD and transmits the converted request to the VBSD. The VBSD transmits the request to a block storage device and returns the response to the Forwarder. The Forwarder replies to the request from the virtual interface with the response from the ABSD. The virtual interface then responds to the virtual machine monitor.

Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

Abstract: A universal transponder interface including: a compartment configured to store a vehicle ignition key; a docking station configured to receive a databus cartridge, wherein the databus cartridge includes codes to support a plurality of different types of databus communication; a first interface configured to connect the universal transponder interface to a vehicle databus; and a second interface configured to connect the universal transponder interface to a vehicle security or remote start system.

Abstract: A memory controller according to the embodiment includes a front-end unit that issues an invalidation command in response to a command from outside of the memory controller, the command including a logical address, an address translation unit that stores a correspondence relationship between the logical and a physical address, an invalidation command processing unit that, when the invalidation command is received, registers the logical address associated with the invalidation command as an invalidation registration region in an invalidation registration unit and issues a notification to the front-end unit, and an internal processing unit that dissolves a correspondence relationship between the logical address registered in the invalidation registration unit and the physical address in the address translation unit in a predetermined order by referencing the logical address registered in the invalidation registration unit.

Abstract: A memory arrangement can store a matrix of matrix data elements specified as index-value pairs that indicate row and column indices and associated values. First split-and-merge circuitry is coupled between the memory arrangement and a first set of FIFO buffers for reading the matrix data elements from the memory arrangement and putting the matrix data elements in the first set of FIFO buffers based on column indices. A pairing circuit is configured to read vector data elements, pair the vector data elements with the matrix data elements, and put the paired matrix and vector data elements in a second set of FIFO buffers based on column indices. Second split-and-merge circuitry is configured to read paired matrix and vector data elements from the second set of FIFO buffers and put the paired matrix and vector data elements in a third set of FIFO buffers based on row indices.

Abstract: A system and method for configuring a filter object for a controller area network is disclosed. The method includes determining, by a processor, a plurality of message identifiers of messages that are to be captured by a filter object. The method also includes performing factorization of a function that represents the plurality of message identifiers to generate a simplified function. The method also includes configuring at least one filter object based on the generated simplified function.

Abstract: A method of managing memory descriptors for a plurality of commands to a non-volatile semiconductor storage device includes requesting memory descriptors from a host system for each of the plurality of commands stored in a first memory, storing the memory descriptors for each of the plurality of commands in free descriptor regions of a plurality of descriptor regions in a second memory of the non-volatile semiconductor storage device, and maintaining a dynamic descriptor list in the second memory for each of the plurality of commands, the dynamic descriptor list for each of the plurality of commands comprising occupied descriptor regions of the plurality of descriptor regions in the second memory having associated memory descriptors. At least one of the occupied descriptor regions includes multiple memory descriptors and a single pointer to a next occupied descriptor region of the plurality of descriptor regions.

Abstract: An inter-die data transfer system includes a receiver circuit in a receiver die coupled to a sender circuit in a sender die through a bus. The receiver circuit includes a safe sample selection circuit and a latency adjustment circuit. The safe sample selection circuit receives from the sender circuit a plurality of training data signals, and determines a safe sample selection signal for a first bit of the bus. The latency adjustment circuit determines a latency adjustment selection signal for the first bit of the bus. A user data safe sample is selected using the safe sample selection signal from a plurality of user data samples associated with a first user data input signal associated with the first bit of the bus. Latency adjustment is performed to the user data safe sample to generate a first user data output signal using the latency adjustment selection signal.

Abstract: Devices are emulated as PCI devices so that existing PCI drivers can be used for the devices. This is accomplished by creating a shim PCI device with a emulated PCI configuration space, accessed via a emulated PCI Extended Configuration Access Mechanism (ECAM) space which is emulated by accesses to trapped unbacked memory addresses. When system software accesses the PCI ECAM space to probe for PCI configuration data or program base address registers of the PCI ECAM space, an exception is raised and the exception is handled by a secure monitor that is executing at a higher privilege level than the system software. The secure monitor in handling the exception emulates the PCI configuration space access of the emulated PCI device corresponding to the ECAM address accessed, such that system software may discover the device and bind and appropriately configure a PCI driver to it with the right IRQ and memory base ranges.

Abstract: An apparatus and method for performing dual concurrent multiplications of packed data elements.

Abstract: A processor includes a decode unit to receive an instruction to indicate a first source packed data operand and a second source packed data operand. The source operands each to include elements. The data elements to include information selected from messages and logical combinations of messages that is sufficient to evaluate: P1(Wj?16 XOR Wj?9 XOR (Wj?3<<<15)) XOR(Wj?13<<<7)XOR Wj?6 P1 is a permutation function, P1(X)=X XOR (X<<<15) XOR (X<<<23). Wj?16, Wj?9, Wj?3, Wj?13, and Wj?6 are messages associated with a compression function of an SM3 hash function. XOR is an exclusive OR operation. <<< is a rotate operation. An execution unit coupled with the decode unit that is operable, in response to the instruction, to store a result packed data in a destination storage location. The result packed data to include a Wj message to be input to a round j of the compression function.

Abstract: A method includes deploying non-volatile random access memory (NVRAM) coupled to a processor or central processing unit (CPU) core of a computing device as a peripheral device via an input/output (I/O) bus, and providing a NVRAM application programming interface (API) for the CPU core to conduct NVRAM read and write operations. Providing the NVRAM API includes allocating a single memory buffer per command to hold data transferred to or from the NVRAM. The method includes configuring the processor in conjunction with the NVRAM API to set up command queues inside in the host Memory Mapped Input Output (MMIO) space.

Abstract: A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

Abstract: A communications system includes a single wire communications bus and a plurality of slave devices, each of the slave devices associated with a common slave identifier. The single wire communications bus is configured to receive a message comprising data, a slave identifier, and a register map address. A respective one of the plurality of slave devices selectively responds to the message if the slave identifier in the message is the same as the common slave identifier associated with the respective one of the plurality of slave devices and the register map address in the message is the same as the register map address associated with the respective one of the plurality of slave devices.

Abstract: Described herein are techniques related to one or more systems, apparatuses, methods, etc. for implementing a location-based power saving solution for docking station products. A wireless docking station communicates with a docking wireless device. The docking station is activated when the docking wireless device is within a pre-configured coverage area of the docking station. The docking station is deactivated when the docking wireless device is outside the pre-configured coverage area.

Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.

Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.