Abstract: A method and system for random number generation. The method comprises the steps of exposing first and second photodetectors to the same mode of a first electromagnetic field in the presence of a mode in a vacuum state of a second electromagnetic field, such that an illumination of the first and second photodetectors is at least substantially balanced; and generating a random noise signal based on a photocurrent difference between the first and second photodetectors.

Abstract: A digital processor, such as, e.g., a divider in a PID controller, performs a mathematical operation such as division (or multiplication) involving operands represented by strings of bit signals and an operator to produce an operation result. The processor is configured by identifying first and second power-of-two approximating values of the operator as the nearest lower and nearest higher power-of-two values to the operator. The operation is performed on the input operands by means of the first and second power-of-two approximating values of the operator by shifting the bit signals in the operands by using the first and second power-of-two approximating values in an alternated sequence to produce: first approximate results by using the first power-of-two approximating value, second approximate results by using the second power-of-two approximating value. The average of the first and second approximate results is representative of the accurate result of the operation.

Abstract: A data processing device according to one aspect of the present invention includes an extractor configured to extract time-series data indicating observed values at points in time in an analysis range from a first point in time to a second point in time, and a first calculator configured to calculate a gradient of a linear function indicating a trend of change in the observed values in the analysis range to minimize an objective function. The objective function indicates a sum of multiplication values at the points in time within the analysis range, the multiplication value is a numerical value obtained by multiplying a square of a difference between a function value of the linear function and the observed value by a weighting coefficient, and the weighting coefficient is a numerical value that increases as an elapsed time from the first point in time to each point in time increases.

Abstract: One embodiment provides a method comprising receiving a plurality of encoded and compressed data blocks, decoding the data blocks, and decompressing the data blocks utilizing a plurality of processor sets. Each processor set is assigned a data block to decompress. The processor sets decompress in parallel to exploit inter-block parallelism. Each processor set comprises one or more processors that collaborate in decompressing an assigned data block to exploit intra-block parallelism. The method further comprises generating a final uncompressed output sequence based on uncompressed data blocks resulting from the decompressing.

Abstract: Arithmetic circuits and methods that perform efficient matrix multiplication for hardware acceleration of neural networks, machine learning, web search and other applications are disclosed herein. Various arrays of multiplier-accumulators may be coupled to form a matrix multiplier which processes data using high precision, fixed point residue number arithmetic.

Abstract: A specialized circuit is configured for floating point computations using numbers represented by a very low precision format (VLP format). The VLP format includes less than sixteen bits and is apportion into a sign bit, exponent bits (e), and mantissa bits (p). The configured specialized circuit is operated to store an approximation of a numeric value in the VLP format, where the approximation is represented as a function of a multiple of a fraction, where the fraction is an inverse of a number of discrete values that can be represented using only the mantissa bits.

Abstract: The disclosed computer-implemented method may include receiving an input value and a floating-point scaling factor and determining (1) an integer scaling factor based on the floating-point scaling factor, (2) a pre-scaling adjustment value representative of a number of places by which to shift a binary representation of the input value prior to a scaling operation, and (3) a post-scaling adjustment value representative of a number of places by which to shift the binary representation of the input value following the scaling operation. The method may further include calculating a scaled result value by (1) shifting rightwards the binary representation of the input value by the pre-scaling adjustment value, (2) scaling the shifted binary representation of the input value by the integer scaling factor, and (3) shifting rightwards the shifted and scaled binary value by the post-scaling adjustment value. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A batched Cholesky decomposition method, system, and non-transitory computer readable medium for a Graphics Processing Unit (GPU), include mirroring a second problem matrix of a second problem to a first problem matrix of a first problem as paired matrices and shifting the second problem matrix by N+1 and combining the first problem matrix and the mirrored second problem matrix into one matrix of (N+1)×N by merging the first problem matrix and the mirrored second problem matrix. The first problem matrix and the second problem matrix are symmetric and positive definite matrices.

Abstract: A digit card calculator is implemented on a touch screen computer. The calculator presents a user input area to receive input of an arithmetic problem. The calculator then presents a workspace area where the digits of the numbers in the arithmetic problem are presented as rectangular digit cards. The digit cards are arranged in place value columns. Bead tokens are presented on digit cards. Each bead token shows or implies the number of beads in the place value of a column. The number of bead tokens on a digit card is equal to the number on the digit card. Individual columns in the arithmetic problem are solved by touching a digit card and moving it down. Carrying in an addition problem is shown by the movement of carry cards. Borrowing in a subtraction problem is shown by the movement of digit tokens from one column to the next.

Abstract: Generating data structures for computer memory. Provisional data structures are generated that respectively have (i) a significand with an initial value of zero and (ii) an exponent that is included in a range of exponents. A test data structure from a provisional data structure by modifying a significand of the first provisional data structure using a significand of a floating-point number such that the significand of the first provisional data structure has a non-zero value. Modifying at least one provisional data structure based on a content of the test data structure. Generating a new data structure that represents the contents of a plurality of provisional-data structures. The plurality of provisional data structures includes at least one provisional data structure that was modified to include the significands of at least two floating-point numbers. The new data structure represents a value that is expressible by a limited number of memory bits.

Abstract: Systems, apparatuses, methods, and computer program products are disclosed for quantum random number generation (QRNG). An example method includes generating, by encoding circuitry of a QRNG chip, a set of time-bin qubits based on a first optical path length. The example method further includes transmitting, by the encoding circuitry of the QRNG chip, the set of time-bin qubits over an optical line. The example method further includes receiving, by decoding circuitry of the QRNG chip, the set of time-bin qubits over the optical line. The example method further includes measuring, by the decoding circuitry of the QRNG chip and based on a second optical path length different from the first optical path length, the set of time-bin qubits to generate a decoded set of bits. In some embodiments, the example method further includes generating, by session authentication circuitry, a session key based on the decoded set of bits.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a circuit configured to perform computations using multiple inputs. The circuit includes multiple adder circuits and a selection circuit that includes multiple input selector. Each adder circuit performs an addition operation using sets of inputs derived from the multiple inputs. The input selectors are configured to select one or more inputs from a set of inputs derived from the multiple inputs based on a sign bit for an input in the set and pass the selected inputs to an adder circuit that generates a sum using the selected inputs. The circuit determines a routing of the sum to another adder circuit based in part on a sign bit for the input in the set of inputs.

Abstract: Technology is described herein for performing multiplication using non-volatile memory cells. A multiplicand may be stored a node that includes multiple non-volatile memory cells. Each memory cell in a node may be programmed to one of two physical states, with each non-volatile memory cell storing a different bit of the multiplicand. Multiplication may be performed by applying a multiply voltage to the node of memory cells and processing memory cell currents from the memory cells in the node. The memory cell current from each memory cell in the node is multiplied by a different power of two. The multiplied signals are summed to generate a “result signal,’ which represents a product of the multiplier and a multiplicand stored in the node. If desired, “binary memory cells” may be used to perform multiplication. Vector/vector and vector/matrix multiplication may also be performed.

Abstract: Apparatus and methods are disclosed for performing block floating-point (BFP) operations, including in implementations of neural networks. All or a portion of one or more matrices or vectors can share one or more common exponents. Techniques are disclosed for selecting the shared common exponents. In some examples of the disclosed technology, a method includes producing BFP representations of matrices or vectors, at least two elements of the respective matrices or vectors sharing a common exponent, performing a mathematical operation on two or more of the plurality of matrices or vectors, and producing an output matrix or vector. Based on the output matrix or vector, one or more updated common exponents are selected, and an updated matrix or vector is produced having some elements that share the updated common exponents.

Abstract: Provided is a device configured to perform a convolution operation. The device includes bi-directional First In First Out memory including bi-directional latches configured to transfer data in a first direction or a second direction depending on a clock signal and connected to each other and performs a convolution operation of an input value and a filter. The device stores first input values corresponding to a window equivalent to a size of the filter from a input value matrix in the bi-directional First In First Out memory in response to a first convolution operation and stores second input values corresponding to a location of the window which is moved in the first direction or the second direction by a predetermined amount from locations of the first input values in the bi-directional First In First Out memory in response to a second convolution operation subsequent to the first convolution operation.

Abstract: The present embodiments relate to circuitry that efficiently performs double-precision floating-point addition operations, single-precision floating-point addition operations, and fixed-point addition operations. Such circuitry may be implemented in specialized processing blocks. If desired, each specialized processing block may efficiently perform a single-precision floating-point addition operation, and multiple specialized processing blocks may be coupled together to perform a double-precision floating-point addition operation. In some embodiments, four specialized processing blocks that are arranged in a one-way cascade chain may compute the sum of two double-precision floating-point number. If desired, two specialized processing blocks that are arranged in a two-way cascade chain may compute the sum of two double-precision floating-point numbers.

Abstract: Methods, systems, and apparatus, including an apparatus for adding three or more floating-point numbers. In one aspect, a method includes receiving, for each of three or more operands, a set of bits that include a floating-point representation of the operand. A given operand is identified. For each other operand, the mantissa bits of the operand are shifted such that the bits of the operand align with the bits of the given operand. A sticky bit for each other operand is determined. An overall sticky bit value is determined based on each sticky bit. The overall sticky bit value is zero whenever all of the sticky bits are zero or at least two sticky bits are non-zero and do not match. The overall sticky bit value matches the value of each non-zero sticky bit whenever all of the non-zero sticky bits match or there is only one non-zero sticky bit.

Abstract: An accelerator for increasing the processing speed of a processor. The accelerator operates in two distinct modes. In a first mode for dense layer processing, row data sets and column data sets are sent to a multiplier for multiplication. In a second mode for sparse layer processing compressed row data sets are received by a row multiplexer and compressed column data sets are received by a column multiplexer. Each multiplexer is configured to compare the indexes of data sets with one another to determine matching indexes. When indexes match, the matching data sets are selected and sent to the multiplier for multiplication. When indexes do not match, data sets are stored in memory devices for subsequent cycles.

Abstract: A method and apparatus for generating harmonics using polynomial non-linear functions. Polynomial functions are used to produce harmonics of an input signal up to a predetermined order, and that match a preferred set of characteristics. The preferred characteristics include approximating a sine function to generate odd harmonics, and using a function with zero slope at ?1, 0, and +1 to generate even harmonics. The polynomial coefficients may be chosen such that most of the coefficients for the odd polynomial function are scaled by the same constant as the coefficients for the even polynomial function, so that the calculation is shared between the two polynomials. In one embodiment, a digital signal processor having a pipelined ALU and a MAC is used to calculate the desired polynomial non-linear functions.

Abstract: An analyzing method and an analyzing system for manufacturing data are provided. The analyzing method includes the following steps. A plurality of models each of which has a correlation value representing a relationship between at least one of a plurality of factors and a target parameter are provided. The models are screened according to the correlation values. A rank information and a frequency information of the factors are listed up according to the models. The factors are screened according to the rank information and the frequency information. The models are ranked and at least one of the models is selected.