Abstract: A method for analyzing an object includes modeling the object with a differential equation, such as a linear partial differential equation (PDE), and sampling data associated with the differential equation. The method uses a probability distribution device to obtain the solution to the differential equation. The method eliminates use of discretization of the differential equation.

Abstract: In an embodiment, a method includes configuring a specialized circuit for floating point computations using numbers represented by a hybrid format, wherein the hybrid format includes a first format and a second format. In the embodiment, the method includes operating the further configured specialized circuit to store an approximation of a numeric value in the first format during a forward pass for training a deep learning network. In the embodiment, the method includes operating the further configured specialized circuit to store an approximation of a second numeric value in the second format during a backward pass for training the deep learning network.

Abstract: An ALU is capable of generating a multiply accumulation by compressing like-magnitude partial products. Given N pairs of multiplier and multiplicand, Booth encoding is used to encode the multipliers into M digits, and M partial products are produced for each pair of with each partial product in a smaller precision than a final product. The partial products resulting from the same encoded multiplier digit position, are summed across all the multiplies to produce a summed partial product. In this manner, the partial product summation operations can be advantageously performed in the smaller precision. The M summed partial products are then summed together with an aggregated fixup vector for sign extension. If the N multipliers equal to a constant, a preliminary fixup vector can be generated based on a predetermined value with adjustment on particular bits, where the predetermined value is determined by the signs of the encoded multiplier digits.

Abstract: Provided is a multi-functional computing apparatus including a multiply-accumulate (MAC) unit having a plurality of MAC circuits, an address generator configured to generate a read address group having a plurality of read addresses, and a memory having a plurality of banks for storing a plurality of read data groups, wherein the address generator delivers the generated read address group to the memory, and the memory delivers a read data group corresponding to the read address group selected from among the plurality of read data groups, the read data group including a plurality of pieces of read data.

Abstract: An electronic device includes one or more processors and memory storing a first logical table for a first time. The first logical table includes a plurality of logical columns, each logical column including an input vector of a plurality of input parameters corresponding to a respective time, and a plurality of logical rows intersecting with the plurality of logical columns, each logical row corresponding to a respective input parameter. The device updates a respective logical column with a first input vector that corresponds to a second time subsequent to the first time, thereby obtaining a second logical table; obtains a first transposed kernel matrix between the second logical table for the second time and the first input vector; determines a first predicted output value for the second time; and outputs the first predicted output value.

Abstract: The present embodiments relate to integrated circuits with circuitry that implements floating-point trigonometric functions. The circuitry may include an approximation circuit that generates an approximation of the output of the trigonometric functions, a storage circuit that stores predetermined output values of the trigonometric functions, and a selector circuit that selects between different possible output values based on a control signal from a control circuit. In some embodiments, the circuitry may include a mapping circuit and a restoration circuit. The mapping circuit may map an input value from an original quadrant of the trigonometric circle to a predetermined input interval, and the restoration circuit may map the output value selected by the selection circuit back to the original quadrant of the trigonometric circle. If desired, the circuitry may be implemented in specialized processing blocks.

Abstract: A true random number generator is provided. The true random number generator includes an Exclusive-Or (XOR) circuit and multiple random entropy source circuits. One entropy source sampling process is performed at an output terminal of each of at least two inverters in each of the multiple random entropy source circuits, which is performed by a flip-flop corresponding to the inverter. Sampling results are inputted to an XOR unit in the random entropy source circuit and XOR processing is performed on the sampling results. XOR processing results outputted by the multiple of random entropy source circuits are inputted to the XOR circuit, and the XOR processing is performed on the XOR processing results to obtain a random number sequence.

Abstract: A method of processing a layer in a convolutional neural network includes reading a plurality of different subsets of pairs of input vector values and corresponding weight vector values from an on-chip memory, storing the pair values in registers of a plurality of multiplication units, simultaneously processing the different subsets of pairs of values in the registers by multiplying the pairs of values and accumulating the results of the multiplications to obtain an output vector for a current layer. The input vector and the weight vector have floating point values and multiplying the pairs of values comprises adding corresponding pairs of integers in a log domain, and an input value or weight value is released from the on-chip memory after said input value or weight value is no longer needed for calculating non-computed output vector values.

Abstract: Multiple random numbers are generated. The multiple random numbers are N different random numbers. N is a positive integer. Generating the multiple random numbers includes generating a random number array including N storage units. The multiple random numbers are shuffled. A random number obtaining instruction is received. A random number is obtained from the multiple random numbers based on the random number obtaining instruction.

Abstract: Systems, methods, and apparatuses relating to performing stencil configuration and computation operations are described.

Abstract: A circuit for transposing a matrix comprising reversal circuitry configured, for each of one or more diagonals of the matrix, to receive elements of the matrix in a first vector and generate a second vector that includes the elements of the matrix in an order that is a reverse of an order of the elements of the matrix in the first vector, and rotation circuitry configured, for each of the one or more diagonals of the matrix, to determine a number of positions by which to rotate the elements of the matrix in the second vector, receive the second vector of elements of the matrix, and generate a third vector that includes the elements of the matrix in the second vector in an order that is a rotation of the elements of the matrix in the second vector by the determined number of positions.

Abstract: In one embodiment, a matrix operation associated with a plurality of input matrices may be performed. The plurality of input matrices may be partitioned into a plurality of input partitions, wherein the plurality of input matrices is partitioned based on a number of available processing elements. The plurality of input partitions may be distributed among a plurality of processing elements, wherein each input partition is distributed to a particular processing element of the plurality of processing elements. A plurality of partial matrix operations may be performed using the plurality of processing elements, and partial matrix data may be transmitted between the plurality of processing elements while performing the plurality of partial matrix operations. A result of the matrix operation may be determined based on the plurality of partial matrix operations.

Abstract: A vector processor includes a coefficient memory and a processor. The processor has an Instruction Set Architecture (ISA), which includes an instruction that approximates a mathematical function by a polynomial. The processor is configured to approximate the mathematical function over an argument, by reading one or more coefficients of the polynomial from the coefficient memory and evaluating the polynomial at the argument using the coefficients.

Abstract: Solving mixed integer problems using a hybrid classical-quantum computing system includes generating a plurality of decision variables for a function associated with a combinatorial optimization problem by a first processor using an optimizer, and deriving at least one quantum state parameter for a quantum processor based upon one or more of the decision variables. The quantum processor is initiated in a quantum state based upon the at least one quantum state parameter. A plurality of intermediate quantum states of the quantum processor are measured using a plurality of quantum measurements of the quantum state to obtain a plurality of samples. The plurality of samples are evaluated by the first processor to obtain a measure of a quality of the quantum state and of one or more solutions to the combinatorial optimization problem.

Abstract: Systems and methods of the present invention provide for one or more server computers communicatively coupled to a network and configured to: receive a request to execute a computational task, including a transformed input used to execute a computational task. A client computer transforms the original input into the transformed input, using an affine mapping where the transformed input is a one-to-one equivalent to the original input (but which can't be inferred by the server computer), and according to a user selection limiting the computational complexity of the mapping according to resource constraints on the client. The server may then execute the computational task and transmit a result to the client to apply an inverse affine mapping, and receive a response which verifies that the computational task result is complete and valid.

Abstract: A method is explained for any adaptive processor processing digital signals by adjusting signal weights on digital signal(s) it handles, to optimize adaptation criteria responsive to a functional purpose or externalities (transient, temporary, situational, and even permanent) of that processor. Adaptation criteria for the adaptive algorithm may be any combination of a signal or parameter estimation, and measured quality(ies). This method performs a linear transformation adapting parameters from M to (M1+L) dimensions in each adaptation event, such that M1 weights are updated without constraints and M0=M?M1 weights are forced by soft constraints into an L-dimensional subspace they spanned at the beginning of the adaptation period. The same dimensionality reduction, using the same linear transformation, is applied to the input data.

Abstract: A method includes receiving an input digital signal and applying the input digital signal to digital filter processing with a corner frequency to produce a filtered output digital signal. The digital filter processing includes a set of multiplication operations using a set of filter multiplication coefficients. The set of multiplication operations is performed by alternately using a first set of approximate multiplication coefficients and a second set of approximate multiplication coefficients different from the first set of approximate multiplication coefficients. The approximate multiplication coefficients in the first set of approximate multiplication coefficients and the second set of approximate multiplication coefficients approximate multiplication coefficients in the set of filter multiplication coefficients as a function of negative power-of-two values. The alternating of multiplication operations results in digital filter processing with average corner frequency approximating the corner frequency.

Abstract: A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.

Abstract: A compute-in-memory (CIM) circuit that enables a multiply-accumulate (MAC) operation based on a current-sensing readout technique. An operational amplifier coupled with a bitline of a column of bitcells included in a memory array of the CIM circuit to cause the bitcells to act like ideal current sources for use in determining an analog voltage value outputted from the operational amplifier for given states stored in the bitcells and for given input activations for the bitcells. The analog voltage value sensed by processing circuitry of the CIM circuit and converted to a digital value to compute a multiply-accumulate (MAC) value.

Abstract: A segment divider, a segment division operation method, and an electronic device are disclosed, relating to the technical field of digital signal processing. The divider includes: a first shift register circuit; a second shift register circuit; a calculation circuit configured to compare data in first registers and data in second registers according to the cascade order, to perform a preset operation and generate an operation result; a third shift register circuit configured to receive and register the operation result bit by bit; then a shift control circuit configured to control the first shift register circuit and the third shift register circuit to perform a shift operation; a counting circuit configured to accumulate the number of shift operations after each shift operation, and send an output signal to finish the operation or send a calculation signal to continue the operation; and an output circuit configured to output a target result.