Abstract: A method and system to transfer a data stream from a data source to a data sink are described herein. The system comprises a trigger core, a plurality of dedicated buffers and a plurality of dedicated buses coupled to the plurality of buffers, trigger core, the data source and the data sink. In response to receiving a request for a data transfer from a data source to a data sink, the trigger core assigns a first buffer and a first bus to the data source for writing data, locks the first buffer and first bus, releases the first buffer and the first bus upon indication from the data source of completion of data transfer to the first buffer, assigns the first buffer and first bus to the data sink for reading data and assigns a second buffer and second bus to the data source for writing data thereby pipelining the data transfer from the data source to the data sink.

Abstract: When an operation mode of an image forming apparatus returns from an energy-saving mode to a regular operation mode, a CPU of a main system outputs a power control signal set to High, and determines the necessariness of information display on an LCD of an operation unit control system to output a starting mode selection signal set to High when the result of the determination is positive. A CPU of the operation unit control system detects the state of a power control signal, and detects mode return from the energy-saving mode depending on the result of the above detection. The CPU of the operation unit control system also detects the state of a starting mode selection signal, and determines the necessariness of information display on the LCD depending on the result of the detection to carry out a display process depending on the result of the determination.

Abstract: A file system adapter card that may be plugged into a host computer system for providing hardware-based file system accesses outside the purview of a host operating system running on the host computer system. The file system adapter card includes a hardware-implemented or hardware-accelerated file service subsystem and a computer bus that permits a host computer system to communicate directly with the file service subsystem for providing file service requests and receiving file service responses. The file service subsystem includes dedicated hardware that operates outside the immediate control of a host operating system, including specialized circuitry for performing at least one major subsystem function.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: A method for addressing system latency within a network system which includes providing a network interface and moving data within each of the plurality of memory access channels independently and in parallel to and from a memory system so that one or more of the plurality of memory access channels operate efficiently in the presence of arbitrary memory latencies across multiple requests is disclosed. The network interface includes a plurality of memory access channels.

Abstract: A signal processing board including a resource board substrate, an external interface on the board substrate, adapted to receive signals for processing, at least one slot adapted to receive a plug-in module with at least one processor thereon and an interface unit adapted to at least participate in converting signals exchanged between the external interface and a processor on a module received by the slot, between a format of signals received by the external interface and a signal format of the processor. The interface unit is suitable to at least participate in the conversion for a plurality of types of processors that differ in the format in which they transmit or receive signals.

Abstract: The power supply device of the present invention supplies power individually to a plurality of disk drives by rendering a plurality of DC/DC converters redundant. One redundant power supply substrate is assigned to a plurality of normal power supply substrates. One redundant power supply substrate supports the outputs of a plurality of normal power supply substrates. The main DC/DC converters in the normal power supply substrate correspond with the subgroups on a one-for-one basis. The secondary DC/DC converters in the redundant power supply substrate each correspond with all of the respective subgroups and are able to supply power to a predetermined single disk drive among the respective disk drives in the subgroups for each of the subgroups.

Abstract: A method for addressing system latency within a network system which includes providing a network interface and moving data within each of the plurality of memory access channels independently and in parallel to and from a memory system so that one or more of the plurality of memory access channels operate efficiently in the presence of arbitrary memory latencies across multiple requests is disclosed. The network interface includes a plurality of memory access channels.

Abstract: Generally, in accordance with embodiments of the present invention, a system having a north bridge and two or more Front Side Buses (FSBs) coupled to the north bridge is provided. The first front side bus has at least a first central processing unit coupled thereto. The second front side bus has at least a second central processing unit coupled thereto.

Abstract: In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

Abstract: A data transmitter includes: a packetization unit receiving primary data from a data processor and packetizing the primary data; a high-speed transmission unit transmitting a data packet obtained from the packetization to a display device in a high-speed mode; and a low-speed transmission unit relaying and transmitting secondary data between the data processor and the display device in a low-speed mode. Accordingly, it is possible to transmit and receive data rapidly and efficiently.

Abstract: A method and apparatus are provided for finding the maxima and minima from a set of inputs data. Given a master set K[0 . . . N?1] of N keys, the current invention can pre-compute a comparison matrix, find the maximum key KMAX or minimum key KMIN from the master set K[0 . . . N?1] and indicate the key position index PMAX of the maximum key or PMIN of the minimum key. Given a subset S[0 . . . M?1] of M keys where the subset S[0 . . . M?1] belongs to the master set K[0 . . . N?1], the current invention can also find the maximum key SMAX or minimum key SMIN from the subset S[0 . . . M?1] and indicate the reference key position index PMAX of the maxima SMAX or PMIN of the minima SMIN in the master set K[0 . . . N?1]. The current invention can also find a specific rank of key (example 5th largest key or 6th smallest key) and return the reference key index position in the master set K[0 . . . N?1].

Abstract: Exemplary embodiments of methods and apparatuses to manage a power of a data processing system are described. One or more constraint parameters of a system are monitored. The data processing system is forced into an idle state for a first portion of a time while allowed to operate for a second portion of the time based on the one or more constraint parameters, wherein the system is forced into the idle state in response to comparing a target idle time to an actual idle time. The target idle time of the system is determined, in one embodiment, based on the one or more constraint parameters. The actual idle time of the system may be monitored to take into account interrupts which disrupt an idle time and idle times resulting from no software instructions to execute. The system may be allowed to operate based on comparisons of the target idle time and the actual idle time.

Abstract: Exemplary embodiments of methods and apparatuses to manage a power of a data processing system are described. A constraint parameter of a system operating at a first frequency and a first voltage is monitored. The system is, based on the monitoring of the constraint parameter, forced into an idle state while operating at a second frequency and a second voltage. The idle state prevents instructions from being executed.

Abstract: In a device that can execute multiple media applications, but only one at a time, a media server coordinates among applications, but neither the media server nor the individual applications maintain rules regarding all of the different applications. Each connection used by an application is assigned a priority and communicates that priority to the media server when the connection is established. When an application requests to begin playback, the request is granted if no other application is playing, or if another application is playing on a connection having a priority at most equal to that of the connection used by the requesting application, but is denied if the connection already in use has a higher priority. Resumption of an application that was interrupted by another application on a connection with higher priority is determined by the interrupted application after the interruption ends, based on information communicated by the media server.

Abstract: A computer-implemented method, apparatus, and computer usable program code are disclosed for migrating a virtual adapter from a source physical adapter to a destination physical adapter in a data processing system where multiple host computer systems share multiple adapters and communicate with those adapters through a PCI switched-fabric bus. The virtual adapter is first caused to stop processing transactions. All in-flight transactions that are associated with the virtual adapter are then captured. The configuration information that defines the virtual adapter is moved from the source physical adapter to the destination physical adapter. The in-flight transactions are then restored to their original locations on the destination virtual adapter. The virtual adapter is then restarted on the destination physical adapter such that the virtual adapter begins processing transactions.

Abstract: Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable loading of a logic value into parallel slave device registers. The communications system includes a slave device having two or more registers, each register having two or more bits, each register configured to load data therein received in accordance with the communications protocol over the data transfer bus in a first configuration, and to load a single logic value into the plurality of bits in a second configuration. A programmable configuration register is configured to be programmed, in accordance with the communications protocol over the data transfer bus, to select two or more of the registers for loading of the single logic value into the two or more of bits of the selected registers in the second configuration.

Abstract: A thin-client terminal (1,1?) according to the invention serves for use in a potentially explosive area (ExB) and has at least the following components: an EDP device (11,11?), which can be programmed using software, has graphics capabilities, has its own storage and computation capacity, is connected, via at least one data transmission channel (K), to a computer (C)—which is not arranged in the potentially explosive area (ExB) and acts as a server—and is capable of communicating with the latter as a thin client in accordance with the client/server principle, and a display (12) which is connected to the EDP device (11, 11?) and is intended to display data. The thin-client terminal (1,1?) according to the invention is explosion-proof or is intrinsically safe and can thus be used in the potentially explosive area (ExB). The thin-client terminal (1,1?) also preferably has an explosion-proof or intrinsically safe keyboard (13) which is connected to the EDP device (11,11?) and is intended for inputting data.

Abstract: In one embodiment of the present invention, a method includes identifying a transaction from a first processor to a second processor of a system with a transaction identifier. The transaction identifier may have a value that is less than or equal to a maximum number of outstanding transactions between the two processors. In such manner, a transaction field for the transaction identifier may be limited to n bits, where the maximum number of outstanding transactions is less than or equal to 2n. In various embodiments, such a transaction identifier combined with a source identifier and a home node identifier may form a globally unique transaction identifier.

Abstract: In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of a communication protocol that provides for cache coherent transactions and non-cache coherent transactions. The switch device includes logic to handle cache coherent transactions from the first semiconductor component to the processor node, while the first semiconductor component does not include such logic. Other embodiments are described and claimed.