Abstract: A block of memory is allocated from a volatile memory device, such as a main system random access memory. The memory block is allocated dynamically and has a dynamically assigned memory address. The memory address of the memory block is shared between a master component executing within an EFI environment and one or more slave components executing within the same and/or different processing modes, such as a system management mode. The memory address is used by the master component to access the memory block and also used by the slave components to access the memory block.

Abstract: A communications arrangement is implemented for packet data communications control. According to an example embodiment of the present invention, a communications arrangement (100), such as a PCI Express type arrangement, carries out separate arbitration functions (112, 116, 117, 118) for ordering packet data. One of the arbitration functions (112) orders the packet data in accordance with protocol standards (e.g., to meet PCI Express standards when implemented with a PCI Express system). The other arbitration function (116, 117, 118) orders the packet data in accordance with performance standards while maintaining compliance with the protocol standards.

Abstract: The invention provides a power switch device for electronic systems equipped having a power module. The power switch device includes a first switch for activating a first signal, a second switch for activating a second signal, a logic judging module for receiving the first and second signals for logic algorithm processing, and a control module electrically connected to the electronic system and the logic judging module. The control module is adapted to generate and transmit on and off signals of the electronic system to the logic judging module. Further, the control module controls switching on the power module according to the off signal and the logic algorithm processing based on the first signal, and also controls switching off the power module according to the on signal and the logic algorithm processing based on the first and second signals.

Abstract: A LINBUS communication network comprises a microcontroller unit containing processing circuitry for performing predefined digital processing functions. LINBUS communication network hardware is located within the microcontroller unit for digitally communicating with an off-chip LINBUS device for transmitting data thereto and receiving data therefrom. A plurality of LINBUS communication network interfaces selectively connects one of a plurality of groups of slave devices to the LINBUS network communications hardware.

Abstract: A processing system includes a plurality of first circuit modules and a wired data bus, connected to the plurality of first circuit modules. A plurality of second circuit modules are coupled to an RF data bus via a millimeter wave communication path. A millimeter wave modem receives first data from at least one of the plurality of first circuit modules via the wired data bus, and transmits the first data over the RF data bus to at least one of the plurality of second circuit modules.

Abstract: A data transfer control device includes: a link controller which analyzes a packet received from a host-side data transfer control device through a serial bus; and an interface circuit which generates interface signals and outputs the generated interface signals to an interface bus. A packet transferred from the host-side data transfer control device through the serial bus includes a synchronization signal code field for setting a synchronization signal code. The interface circuit generates synchronization signals FPFRAME and FPLINE included in the interface signals based on the synchronization signal code set in the packet.

Abstract: A method of notifying clients of a change in a USB including a first client requesting notification of a first change in the USB, detecting the first change in the USB, and notifying the first client requesting notification that the first change in the USB occurred.

Abstract: Managing Message Signaled Interrupts (MSIs). For example, a method of managing MSI requests in a computing system may include receiving a plurality of MSI requests from one or more components of the computing system; directing data of the plurality of MSI requests to be stored sequentially, according to a First In First Out (FIFO) order, in successive entries of a FIFO structure defined in a main memory of the computing system; and directing a processor of the computing system to retrieve data of one or more of the plurality of MSI requests from the FIFO structure to be processed according to the FIFO order. Other embodiments are described and claimed.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: A method for distributing interrupt load to processors in a multiprocessor system. The method includes executing current transactions with multiple processors (104, 106, 108) where each transaction is associated with one of the processors, generating an interrupt request, estimating a transaction completion time for each processor and directing the interrupt request (102) to the processor having the least estimated transaction completion time. Estimating a transaction completion time occurs periodically so that information pertaining to transaction times is stored and continually updated. According to one aspect of the invention, the step of estimating a transaction completion time for each processor occurs when the interrupt request is generated. According to another aspect of the invention, the step of communicating the interrupt request includes communicating the interrupt request to an intermediary processor prior to estimating the transaction completion time.

Abstract: In accordance with an aspect of the present invention, a slave device enters a state suitable for establishing communication with a host device only if additional information is received on a serial bus after receiving a reset signal on the same bus. Such a feature may avoid or reduce disruption to applications executing on a slave device when false reset signals are received, for example, when the slave device is connected to a dumb charger on a USB interface for charging.

Abstract: In a device, such as a cell phone, memory resource sharing is enabled between components, such as integrated circuits, each of which has memory resources. This may be accomplished by providing an interconnect between the components and constructing transaction units which are sent over the interconnect to initiate memory access operations. The approach may also be used to allow for a degree of communication between device components.

Abstract: An apparatus and method are provided that include providing a transaction data structure, and monitoring the transaction data structure for a predetermined amount of time. A link between a bus device and a host controller may be provided into a low power state in response to the monitored transaction data structure.

Abstract: Apparatus, systems, and methods for coupling Fiber Channel (FC) storage devices and serial attached SCSI (SAS) storage device to a computer system through a single host bus adapter (HBA). The HBA includes a SAS storage controller four coupling to one or more SAS storage devices and an FC interface for coupling to one or more FC storage devices. The HBA also includes translation logic to translate information exchanged between the SAS storage controller and the FC storage device(s). Translation may include translation of addressing information between FC protocols and formats used by the SAS storage controller, may include use of a buffer to enable exchanges at different data rates, and may include use of a buffer to aggregate an inbound FC multiframe sequence into a single data buffer for use by the SAS storage controller.

Abstract: The present invention relates to an air conditioner and a method of operating the same. The air conditioner includes a human body detection unit configured to rotatably operate and to detect a person within an indoor area, a position determination unit configured to determine a position of the person using data detected by the human body detection unit and to set a reference area to which a current of air will be provided according to a frequency of detection on the person, and a control unit configured to control the human body detection unit so that the human body detection unit detects the person by a reference frequency or more and to control the current of air based on the determination results by the position determination unit so that the current of air is discharged toward the reference area.

Abstract: A medical device system includes a portable medical device and a docking unit on which the medical device can be removably mounted. The docking unit is configured to communicate with a controller of the medical device when the medical device is mounted on the docking unit to instruct the controller to execute a selected program.

Abstract: The invention pertains to a modular data transmission system with several modules or bus nodes that can be arranged adjacent to one another in a row. The data transmission system comprises a first bus node that features a first transmitter for the wireless transmission of data and an electrical connector, as well as a second bus node that features a first receiver for the wireless reception of data and an electrical connector. Both bus nodes are detachably fixed on a mounting rail such that they are arranged adjacent to one another in a row. The first and second bus nodes are respectively detachably connected to a bus receptacle, wherein each bus receptacle features an electrical mating connector that is coupled to the electrical connector of the respective bus node in the connected state in order to transmit energy, as well as a positioning device for positioning the respective bus node.

Abstract: A method and device for controlling slave devices with a master device. The device performs specific functions to control operations of slave devices with a master device, and includes a user input receiving unit that receives an input from a user, a memory unit that stores command sets, each command set corresponding to a series of operation controls of the master device or one of the slave devices, and a control unit that generates operation control signals of the master device or one of the slave devices when an operation control command set is selected, the operation control signals corresponding to the selected operation control command set.

Abstract: A computer-implemented method, apparatus, and computer program product are disclosed in a data processing environment that includes host computer systems that are coupled to adapters utilizing a switched fabric for routing packets between the host computer systems and the adapters. A unique destination identifier is assigned to one of the host computer systems. A portion of a standard format packet destination address is selected. Within a particular packet, the portion is set equal to the unique identifier that is assigned to the host computer system. The particular packet is then routed through the fabric to the host computer system using the unique destination identifier.

Abstract: Described is an electronics enclosure having a midplane, a first field-replaceable CPU (central processing unit) module, and a second field-replaceable CPU module. Each CPU module is independently pluggable into and removable from the midplane. Each CPU module is configurable into either one of a first configuration and a second configuration, wherein the CPU modules operate independently as separate CPU modules when configured according to the first configuration and cooperate as a unitary CPU module when configured according to the second configuration.