Patents Examined by Colleen E Snow
  • Patent number: 11569088
    Abstract: Methods of enhancing selective deposition are described. In some embodiments, a passivation layer is deposited on a metal surface before deposition of a dielectric material. A block I molecule is deposited on a metal surface, and a block II molecule is reacted with the block I molecule to form a passivation layer.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: January 31, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Yong Wang, Andrea Leoncini, Doreen Wei Ying Yong, John Sudijono
  • Patent number: 11569183
    Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: January 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yu Kuo, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Yi-Yang Lei, Wei-Jie Huang
  • Patent number: 11557734
    Abstract: An organic electroluminescence device includes a first electrode, a second electrode, and an emission layer disposed between the first electrode and the second electrode, wherein the emission layer includes a polycyclic compound having a fused ring system and represented by Formula 1 to achieve high efficiency and improved efficiency drop characteristics in an emission wavelength range:
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: January 17, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ryuhei Furue, Hirokazu Kuwabara
  • Patent number: 11545579
    Abstract: Many of the physical properties of a silicon semiconductor have already been understood, whereas many of the physical properties of an oxide semiconductor have been still unclear. In particular, an adverse effect of an impurity on an oxide semiconductor has been still unclear. In view of the above, a structure is disclosed in which an impurity that influences electrical characteristics of a semiconductor device including an oxide semiconductor layer is prevented or is eliminated. A semiconductor device which includes a gate electrode, an oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer and in which the nitrogen concentration in the oxide semiconductor layer is 1×1020 atoms/cm3 or less is provided.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: January 3, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Tetsunori Maruyama, Yuki Imoto
  • Patent number: 11532649
    Abstract: Provided is a display device including: a capacitor having a first electrode, a first insulating film over the first electrode, and a second electrode over the first insulating film; and a first transistor over the capacitor. The first transistor includes the second electrode a second insulating film over the second electrode, an oxide semiconductor film over the second insulating film, and a first source electrode and a first drain electrode over the oxide semiconductor film. The first source electrode and the first drain electrode are electrically connected to the oxide semiconductor film.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: December 20, 2022
    Assignee: Japan Display Inc.
    Inventors: Tetsuo Morita, Hiroyuki Kimura, Makoto Shibusawa, Hiroshi Tabatake, Yasuhiro Ogawa
  • Patent number: 11527726
    Abstract: An organic electroluminescence device including a first electrode, a second electrode, and an emission layer between the first electrode and the second electrode, wherein the emission layer includes a compound represented by Formula 1 to achieve high efficiency and an improved efficiency drop in a deep blue emission wavelength region:
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: December 13, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ryuhei Furue, Hirokazu Kuwabara, Nobutaka Akashi
  • Patent number: 11527728
    Abstract: The present disclosure relates to organic electroluminescent compounds, and a host material, an electron buffer material, an electron transport material and an organic electroluminescent device comprising the same. By using the organic electroluminescent compounds of the present disclosure, the organic electroluminescent device secures fast electron current properties by intermolecular stacking and interaction, and thus, it is possible to provide the organic electroluminescent device having low driving voltage and/or excellent luminous efficiency and/or efficient lifespan properties.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: December 13, 2022
    Inventor: Hee-Choon Ahn
  • Patent number: 11522147
    Abstract: The present application discloses an organic light-emitting device and a display device, which include a light-emitting layer. The light-emitting layer includes a donor light-emitting layer and an acceptor light-emitting layer, wherein at least one film layer of the donor light-emitting layer and the acceptor light-emitting layer adopts a thermally activated delayed material.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: December 6, 2022
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Fang Wang
  • Patent number: 11521894
    Abstract: Contact designs for semiconductor FET devices are provided. In one aspect, a contact structure includes: a metal line(s); a first ILD surrounding the metal line(s), wherein a top surface of the first ILD is recessed below a top surface of the metal line(s); a liner disposed on the first ILD and on portions of the metal line(s); a top contact(s) disposed over, and in direct contact with, the metal line(s), wherein an upper portion of the top contact(s) has a width W1 and a height H1, wherein a lower portion of the top contact(s) has a width W2 and a height H2, and wherein W1<W2 and H1>H2; and a second ILD disposed over the liner and surrounding the top contact(s). A semiconductor FET device and methods for fabrication thereof are also provided.
    Type: Grant
    Filed: July 18, 2020
    Date of Patent: December 6, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Julien Frougier, Ekmini Anuja De Silva, Eric Miller
  • Patent number: 11515198
    Abstract: Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with dielectric material comprising silicon, oxygen and carbon. The carbon is present to a concentration within a range of from about 3 atomic percent to about 20 atomic percent. Some embodiments include a method of providing dielectric fill across a semiconductor construction having an opening extending therein. The semiconductor construction has an upper surface proximate the opening. The method includes forming photopatternable dielectric material within the opening and across the upper surface, and exposing the photopatternable dielectric material to patterned actinic radiation.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: November 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Scott L. Light, John A. Smythe, Sony Varghese
  • Patent number: 11456177
    Abstract: A method of manufacturing a semiconductor device is provided. A precursor structure is formed, in which the precursor structure includes a patterned substrate having at least one trench therein, an oxide layer covering the patterned substrate, and a nitride layer on the oxide layer and exposing a portion of the oxide layer in the trench. A first barrier layer and a first gate structure is formed on the oxide layer. A portion of the first barrier layer is removed with an etchant including CF4, C2F6, C3F8, C4F8, F2, NF3, SF6, CHF3, HF, COF2, ClF3 or H2O2 to expose a sidewall of the oxide layer. A second barrier layer is formed on the first gate structure and the oxide layer. A portion of the second barrier layer is removed with the etchant. A second gate structure is formed on the second barrier layer.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: September 27, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Jen-I Lai, Chun-Heng Wu, Rou-Wei Wang
  • Patent number: 11456286
    Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: September 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Chan Yoo, Todd O. Bolken
  • Patent number: 11450837
    Abstract: A display device includes: a substrate including a display area, a first non-display area, a second non-display area, and a bending area; a display element disposed on a surface of the substrate; a resin layer disposed on another surface of the substrate to correspond to the display area, where the resin layer exposes at least a portion of the another surface; an external light-absorbing layer disposed on the another surface exposed by the resin layer; and a first protective layer disposed on the another surface of the substrate to correspond to the first non-display area.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: September 20, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ungsoo Lee, Seungwook Kwon, Kibeom Lee, Sooyoun Kim, Wooyong Sung, Seoyeon Lee, Hyoungsub Lee, Moonwon Chang
  • Patent number: 11437580
    Abstract: A polymer comprising wherein Ar1 and Ar2 are optional and either the same or different and independently selected from an aryl group or an heteroaryl group. In this polymer, W is selected from the group consisting of: S, Se, O, and N-Q; and Q is selected from the group consisting of: a straight-chain or branched carbyl, silyl, or hydrocarbyl, a branched or cyclic alkyl with 1 to 30 atoms, a fused substituted aromatic ring, and a fused unsubstituted aromatic ring. Additionally, in the polymer, R4 and R5 are selected from the group consisting of: a straight-chain or branched carbyl, silyl, or hydrocarbyl, a branched or cyclic alkyl with 1 to 30 atoms, a fused substituted aromatic ring, and a fused unsubstituted aromatic ring; and x+y=1.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: September 6, 2022
    Assignee: Phillips 66 Company
    Inventors: Hualong Pan, Kathy Woody
  • Patent number: 11437299
    Abstract: A semiconductor apparatus comprising a first substrate that has a first surface and a second surface and is provided with a through hole extending through from the first surface to the second surface and an insulating layer and a conductive member that are provided in the through hole is provided. The through hole includes a first opening formed in the first substrate and a second opening provided between the first opening and the second surface. The first opening and the second opening each have a tapered shape whose opening width decreases from the first surface to the second surface, and a first taper angle formed by a side surface of the first opening and a plane parallel to the second surface is smaller than a second taper angle formed by a side surface of the second opening and a plane parallel to the second surface.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: September 6, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Tatsuya Saito
  • Patent number: 11424157
    Abstract: A method of manufacturing a structure that includes a substrate provided with a through hole, and a resin layer provided on a front surface of the substrate to close the through hole, includes, in order, preparing the substrate including the through hole and including a support substrate on a back surface of the substrate to close the through hole, bonding a dry film to a front surface of the substrate, the dry film including a support member and a resin layer on the support member, to close the through hole with the resin layer and turn the through hole into a closed space with the substrate, the support substrate, and the dry film, opening the through hole turned into the closed space from the support substrate side, and separating the support member from the dry film while retaining the resin layer on the front surface of the substrate.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: August 23, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Seiichiro Yaginuma, Ryotaro Murakami, Hideomi Kumano, Masahisa Watanabe, Tetsushi Ishikawa
  • Patent number: 11417650
    Abstract: An integrated circuit including a substrate, a first semiconductor element, and a second semiconductor element is provided. The substrate has a high voltage region and a low voltage region separated from each other. The first semiconductor element is located in the high voltage region. The first semiconductor element includes a first oxide layer and a first gate. The first oxide layer is embedded in the substrate. The first gate is located on the first oxide layer. The first gate is a polycrystalline gate. The second semiconductor element is located in the low voltage region. The second semiconductor element includes a second oxide layer and a second gate. The second oxide layer is embedded in the substrate. The second gate is located on the second oxide layer. The second gate is a metal gate. A manufacturing method of an integrated circuit is also provided.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: August 16, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Chieh Pu, Jih-Wen Chou, Chih-Chung Tai
  • Patent number: 11411086
    Abstract: An integrated chip includes a field plate overlying an isolation structure. A gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an upper surface of the gate electrode to a front-side of the substrate. The etch stop layer overlies a drift region disposed between the source region and the drain region. The field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate extends from a top surface of the first ILD layer to an upper surface of the etch stop layer. The isolation structure is disposed within the substrate and extends from the front-side of the substrate to a point below the front-side of the substrate. The isolation structure is disposed laterally between the gate electrode and the drain region.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: August 9, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kaochao Chen, Chia-Cheng Ho, Ming Chyi Liu
  • Patent number: 11410881
    Abstract: Methods of forming copper interconnects are described. A doped tantalum nitride layer formed on a copper layer on a substrate has a first amount of dopant. The doped tantalum nitride layer is exposed to a plasma comprising one or more of helium or neon to form a treated doped tantalum nitride layer with a decreased amount of dopant. Apparatus for performing the methods are also described.
    Type: Grant
    Filed: June 28, 2020
    Date of Patent: August 9, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Rui Li, Xiangjin Xie, Tae Hong Ha, Xianmin Tang, Lu Chen
  • Patent number: 11404462
    Abstract: Image quality of an imaging element having a configuration in which pixels having color filters are arranged two-dimensionally is prevented from being lowered. An imaging element includes a plurality of pixels and incident light attenuation sections. The pixel includes a color filter transmitting incident light having a predetermined wavelength, and a photoelectric conversion section that produces an electric charge according to the light transmitted through the color filter. The incident light attenuation section is disposed between the color filters of the adjacent pixels, is configured to be different in surface height from the color filters, and attenuates light not transmitted through the color filter but incident on the photoelectric conversion section of the pixel where the color filter is disposed.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: August 2, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yuichi Seki, Yoichi Ootsuka