Patents Examined by Colleen E Snow
  • Patent number: 12652975
    Abstract: A semiconductor device has a semiconductor base substrate, a first electrode disposed on the surface of the semiconductor base substrate, a protective film covering an end portion of the first electrode, and a second electrode disposed on the first electrode, in an opening of the protective film. The protective film has an end portion where the protective film and the second electrode overlap. In a plan view of the semiconductor device, the end portion has a convex portion with a first radius of curvature and a concave portion with a second radius of curvature. The convex portion protrudes in a direction away from the opening, and the convex portion is recessed toward the opening. The first radius of curvature is larger than the second radius of curvature.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: June 9, 2026
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuyuki Hoshi
  • Patent number: 12648256
    Abstract: In one aspect, a preparation method for a solar cell includes the following steps: sequentially forming a first silicon oxide layer, an intrinsic amorphous silicon layer, a phosphorosilicate glass layer and a second silicon oxide layer on the back surface of an n-type silicon substrate; removing the phosphorosilicate glass layer and the second silicon oxide layer in a partial region of the back surface of the n-type silicon substrate; subjecting the back surface of the n-type silicon substrate to boron diffusion; forming an isolation groove at the boundary between the boron-doped polycrystalline silicon layer and the phosphorus-doped polycrystalline silicon layer; and preparing a first electrode connected to the boron-doped polycrystalline silicon layer and a second electrode connected to the phosphorus-doped polycrystalline silicon layer.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: June 2, 2026
    Assignee: TONGWEI SOLAR (CHENGDU) CO., LTD.
    Inventors: Peng Zhang, Xiajie Meng, Guoqiang Xing
  • Patent number: 12635510
    Abstract: A method for forming an interconnect structure in an element is disclosed. The method can include patterning a cavity in a non-conductive material. The method can include exposing a surface of the cavity in the non-conductive material to a surface nitriding treatment. The method can include depositing a conductive material directly onto the treated surface after the exposing.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: May 19, 2026
    Assignee: Adeia Semiconductor Technologies LLC
    Inventors: Cyprian Emeka Uzoh, Laura Wills Mirkarimi
  • Patent number: 12628399
    Abstract: Disclosed are methods and systems for depositing layers comprising a Group 13 element on a surface of a substrate via contacting the substrate with at least a vapor-phase first precursor and a vapor-phase second precursor comprising an alkyl halide. Exemplary structures in which the layers may be incorporated include field effect transistors, VNAND cells, and metal-insulator-metal (MIM).
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: May 12, 2026
    Assignee: ASM IP Holding B.V.
    Inventors: Charles Dezelah, Petro Deminskyi, Qi Xie
  • Patent number: 12628609
    Abstract: A method includes receiving, by a processing device, first data generated by a first sensor of a substrate processing system. The first data is generated responsive to the first sensor receiving electromagnetic radiation from a substrate held by a robot arm of a transfer chamber in the substrate processing system. The method further includes processing the first data to obtain second data. The second data includes a first indication of performance of the substrate processing system. The method further includes causing, in view of the second data, performance of a corrective actions associated with the substrate processing system.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: May 12, 2026
    Assignee: Applied Materials, Inc.
    Inventors: Tapashree Roy, Todd Egan, Viswanath Bavigadda, Nitin Gupta
  • Patent number: 12604507
    Abstract: A method of manufacturing a semiconductor device includes: forming a silicon oxide film covering each of a first main surface and a second main surface of a semiconductor substrate; forming a redistribution wiring on the first main surface side of the semiconductor substrate; and grinding the second main surface of the semiconductor substrate. This grinding step is performed in a state in which a thickness of the silicon oxide film positioned on the second main surface is equal to or larger than 10 nm and equal to or smaller than 30 nm.
    Type: Grant
    Filed: March 16, 2023
    Date of Patent: April 14, 2026
    Assignee: Renesas Electronics Corporation
    Inventors: Futoshi Komatsu, Tomoo Nakayama, Katsuhiro Uchimura, Hiroshi Inagawa
  • Patent number: 12598848
    Abstract: The present disclosure relates to a method for manufacturing a semiconductor light emitting device through non-wire bonding, the method comprising the steps of: preparing a semiconductor light emitting die and a support substrate; attaching the semiconductor light emitting die to the support substrate while a second electrical path is exposed, the semiconductor light emitting die being attached such that a conductive bonding structure covering the entire second semiconductor region is tightly bonded to a bonding layer; removing the substrate; and electrically connecting the second electrical path to the remaining semiconductor region among a first semiconductor region and the second semiconductor region through electrical connection through deposition.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: April 7, 2026
    Assignee: WAVELORD CO., LTD
    Inventor: Sang Jeong An
  • Patent number: 12588287
    Abstract: Provided is a display device including: a capacitor having a first electrode, a first insulating film over the first electrode, and a second electrode over the first insulating film; and a first transistor over the capacitor. The first transistor includes the second electrode, a second insulating film over the second electrode, an oxide semiconductor film over the second insulating film, and a first source electrode and a first drain electrode over the oxide semiconductor film. The first source electrode and the first drain electrode are electrically connected to the oxide semiconductor film.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: March 24, 2026
    Assignee: Magnolia White Corporation
    Inventors: Tetsuo Morita, Hiroyuki Kimura, Makoto Shibusawa, Hiroshi Tabatake, Yasuhiro Ogawa
  • Patent number: 12575391
    Abstract: A method for fabricating semiconductor devices is disclosed. The method includes forming a stack on a first substrate. A laser liftoff layer is interposed between the stack and the first substrate. The method includes forming a plurality of first interconnect structures over a first side of the stack. The method includes attaching a second substrate to the stack on the first side, with the plurality of first interconnect structures interposed between the stack and the second substrate; removing the first substrate by applying radiation on the laser liftoff layer. The method includes forming a plurality of second interconnect structures on a second side of the stack opposite to the first side.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: March 10, 2026
    Assignee: Tokyo Electron Limited
    Inventors: Soo Doo Chae, Arkalgud Sitaram
  • Patent number: 12557533
    Abstract: The present disclosure relates to a display panel and a display device thereof. The display panel includes: a substrate; an organic light-emitting device located on the substrate; a cover layer located on the organic light-emitting device; a light extraction layer located on the cover layer; an optical functional layer located on the light extraction layer; and an encapsulation layer located on the optical functional layer. A refractive index of the light extraction layer is less than a refractive index of the cover layer and less than a refractive index of a portion of the encapsulation layer closest to the optical functional layer. A refractive index of the optical functional layer is less than the refractive index of the portion of the encapsulation layer closest to the optical functional layer and not equal to the refractive index of the light extraction layer.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: February 17, 2026
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Baoke He, Duanming Li, Minghao Gao, Qin Zhang, Quanqin Sun
  • Patent number: 12550702
    Abstract: A semiconductor device comprises a III-N device including an insulating substrate. The insulating substrate includes a first side and a second side. The device further includes a III-N material structure on a first side of the insulating substrate, and a gate electrode, a source electrode, and a drain electrode on a side of the III-N material structure opposite the substrate. A backmetal layer on the second side of the insulating substrate, and a via hole is formed through the III-N material structure and the insulating substrate. A metal formed in the via-hole is electrically connected to the drain electrode on the first side of the substrate and electrically connected to the backmetal layer on the second side of the substrate.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: February 10, 2026
    Assignee: Transphorm Technology, Inc.
    Inventors: Geetak Gupta, Umesh Mishra, Davide Bisi, David Michael Rhodes, Rakesh K. Lal, Carl Joseph Neufeld
  • Patent number: 12550391
    Abstract: A semiconductor apparatus having a staggered structure, a method of manufacturing a semiconductor apparatus, and an electronic device including the semiconductor apparatus. The semiconductor apparatus includes a first element and a second element on a substrate. The first element and the second element each include a comb-shaped structure. The comb-shaped structure includes a first portion extending in a vertical direction relative to the substrate, and at least one second portion extending from the first portion in a lateral direction relative to the substrate and spaced from the substrate. A height of the second portion of the first element in the vertical direction is staggered with respect to a height of the second portion of the second element in the vertical direction. A material of the comb-shaped structure of the first element is different from a material of the comb-shaped structure of the second element.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: February 10, 2026
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huilong Zhu, Xuezheng Ai, Yongkui Zhang
  • Patent number: 12527210
    Abstract: A display device includes a display panel, a sensor layer provided on the display panel, and a light control layer provided on the sensor layer, and including at least one of a dye or a pigment, wherein the display panel includes a base layer, a pixel-defining film provided on the base layer and having an opening defined therein, a light-emitting element including a light-emitting layer provided in the opening, an inorganic deposition layer provided on the light-emitting element, a low refractive pattern layer provided on the pixel-defining film, and an encapsulation layer provided on the low refractive pattern layer and the inorganic deposition layer, and the encapsulation layer has a higher refractive index than the low refractive pattern layer. Accordingly, due to improved light collection efficiency of the light-emitting element, the display device may have improved display efficiency.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: January 13, 2026
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hongyeon Lee, Ohjeong Kwon, Seungyeon Jeong, Hyeoji Kang, Taeho Kim
  • Patent number: 12520544
    Abstract: A method for forming a nanostructure array and a field effect transistor device on a substrate are provided. The method for forming the nanostructure array includes: providing a template solution comprising template nanostructures; depositing at least one template nanostructure onto the substrate by contacting the template solution with the substrate; and forming on the substrate at least one fixation structure each intersecting with all or a portion of the at least one template nanostructure to fix all or a portion of the at least one template nanostructure on the substrate.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: January 6, 2026
    Assignee: PEKING UNIVERSITY
    Inventors: Wei Sun, Mengyu Zhao
  • Patent number: 12507431
    Abstract: A semiconductor structure includes semiconductor layers stacked vertically over a substrate. The structure includes a gate structure interleaved with the semiconductor layers, where the gate structure wraps around a first end portion of each semiconductor layer. The structure includes dielectric layers stacked vertically over the substrate and interleaved with the semiconductor layers, where a first end portion of each dielectric layer is aligned with a second end portion of each semiconductor layer, which is laterally opposite to the first end portion of each semiconductor layer. The structure includes a metal contact extending vertically to contact the second end portion of each semiconductor layer.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: December 23, 2025
    Assignee: Tokyo Electron Limited
    Inventors: H. Jim Fulford, Mark I. Gardner
  • Patent number: 12482679
    Abstract: A method of transferring a die from a carrier to a receive substrate is provided. The method includes the steps of: (a) supporting a die on a carrier, a transfer material being provided between the die and the carrier; (b) exposing the transfer material to light energy to form a bubble in the transfer material; and (c) transferring the die from the carrier to a receive substrate using the bubble, the die being in contact with the bubble when the die contacts the receive substrate.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: November 25, 2025
    Assignee: Kulicke and Soffa Industries, Inc.
    Inventor: Val R. Marinov
  • Patent number: 12469787
    Abstract: A semiconductor element includes a conductive pad. The semiconductor element further includes a first layer of a first polyimide material having an uppermost surface. The first layer includes a via trench extending through the first layer from the uppermost surface to the conductive pad. The semiconductor element further includes a second layer of a second polyimide material arranged in direct contact with the uppermost surface. The second layer includes a line trench extending to the uppermost surface. The semiconductor element further includes a conductive structure arranged in the via trench and the line trench such that copper is in direct contact with the second polyimide material.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: November 11, 2025
    Assignee: International Business Machines Corporation
    Inventors: Mukta Ghate Farooq, James J. Kelly, Eric Perfecto, Spyridon Skordas, Dale Curtis McHerron
  • Patent number: 12456682
    Abstract: An apparatus, a method, and a method of manufacturing an integrated circuit having a metal layer, metal wires within the metal layer being configured such that they have a regular pattern.
    Type: Grant
    Filed: February 13, 2021
    Date of Patent: October 28, 2025
    Assignee: Arm Limited
    Inventors: Marlin Wayne Frederick, Jr., Karen Lee Delk
  • Patent number: 12439668
    Abstract: An integrated chip includes a gate structure overlying a substrate between a source region and a drain region. A field plate is disposed within a first dielectric layer overlying the substrate. The field plate is laterally offset from the gate structure by a non-zero distance in a direction towards the drain region. An isolation structure is disposed within the substrate. The field plate directly overlies at least a portion of the isolation structure.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: October 7, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kaochao Chen, Chia-Cheng Ho, Ming Chyi Liu
  • Patent number: 12426498
    Abstract: An electron barrier film for a quantum dot light-emitting diode, the electron barrier film includes: a compound with a general formula R1—Si(OR2)3; or a raw material for forming the electron barrier film includes a compound with the general formula R1—Si(OR2)3 one in a group. Not only can a rate of injecting electrons into the luminescent layer be adjusted, so that the number of electron holes in the quantum dot luminescent layer can be equal to the number of electrons in the quantum dot luminescent layer, and a recombination efficiency of the electrons and the electron holes in the luminescent layer is improved, a better interface modification effect can also be achieved, and a surface roughness of the quantum dot luminescent layer is reduced, so that an overall performance of the quantum dot light-emitting diode is more stable.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: September 23, 2025
    Assignee: TCL TECHNOLOGY GROUP CORPORATION
    Inventor: Xue Li