Patents Examined by Colleen E Snow
  • Patent number: 11670529
    Abstract: A substrate processing device according to the present invention is a substrate processing device that performs substrate processing with a processing solution and includes inspection means for inspecting degradation of components constituting the substrate processing device. The inspection means includes: capturing means for acquiring image data of the components; color information acquisition means for acquiring color information of an inspection target component from the image data acquired by the capturing means; and degradation determination means for determining a degradation degree of the inspection target component based on the acquired color information.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: June 6, 2023
    Assignee: SCREEN HOLDINGS CO., LTD.
    Inventor: Akio Hashizume
  • Patent number: 11658024
    Abstract: A semiconductor device and a method of manufacturing the semiconductor device are included. The method of manufacturing the semiconductor device includes forming a hafnium oxide layer on a substrate and crystallizing the hafnium oxide layer by using a hafnium cobalt oxide layer as a seed layer. According to the method of manufacturing the semiconductor device, a thin-film hafnium oxide layer may be easily crystallized.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: May 23, 2023
    Assignee: Samsung Electronics Co.. Ltd.
    Inventors: Jeonggyu Song, Kyooho Jung, Yongsung Kim, Jeongil Bang, Jooho Lee, Junghwa Kim, Haeryong Kim, Myoungho Jeong
  • Patent number: 11658077
    Abstract: According to one embodiment, a method for manufacturing a semiconductor member is disclosed. The method can include measuring a first mass of a semiconductor substrate including a first semiconductor layer of a first conductivity type. The method can include forming a first opening in an upper surface of the first semiconductor layer. The method can include measuring a second mass of the semiconductor substrate in which the first opening is formed. In addition, the method can include when forming a second semiconductor layer of a second conductivity type in the first opening, changing an impurity concentration of the second conductivity type in the second semiconductor layer according to a difference in mass between the first mass and the second mass.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: May 23, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Noboru Yokoyama, Kazuyuki Sato
  • Patent number: 11651968
    Abstract: A method for forming a planarization layer includes: providing a substrate including a trench; coating a pre-thinner over a surface of the trench; forming a gap-filling material in the trench; coating a post-thinner over the gap-filling material; and performing a spinning process to rotate the substrate.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: May 16, 2023
    Assignee: SK hynix Inc.
    Inventors: Ji Sok Lee, Sung Koo Lee, Jae Hee Sim
  • Patent number: 11629988
    Abstract: A flow sensor includes a semiconductor, an electric control circuit, a lead frame, and a spacer. The spacer is disposed in a clearance between the lead frame and the semiconductor device on an opposite side from a joint portion of the semiconductor device with the lead frame on a side of the electric control circuit across the diaphragm disposed therebetween. A surface of the electric control circuit and a part of a surface of the semiconductor device is covered with resin while the air flow sensing unit is exposed. At the joint portion, the semiconductor device is attached to the lead frame via an adhesive.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: April 18, 2023
    Assignee: Hitachi Astemo, Ltd.
    Inventors: Tsutomu Kono, Yuuki Okamoto, Takeshi Morino, Keiji Hanzawa
  • Patent number: 11626420
    Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes in the memory cell region and the connection region, a plurality of channel structures passing through the plurality of gate electrodes and extending in a vertical direction in the memory cell region, and a plurality of pad layers extending in a first direction from each of the plurality of gate electrodes in the connection region. The plurality of pad layers is disposed in a stepped form in a second direction. The device further includes a plurality of dummy lines arranged in one row in the first direction between two pad layers adjacent to each other in the second direction and disposed apart from one another with a pad connection region therebetween in the first direction. The pad connection region overlaps two pad layers successively disposed in the first direction.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: April 11, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Jin Jung, So-Ra Kim, Bong-Tae Park
  • Patent number: 11618754
    Abstract: The present disclosure provides a nitrogen-containing compound, and an electronic component and an electronic device including the same, and belongs to the technical field of organic electroluminescence. The nitrogen-containing compound provided by the present disclosure has polycyclic conjugation properties, the compound has a core structure of fused indolocarbazole. The bond energy between the atoms is high, thus the compound has a good thermal stability, and facilitates solid state accumulation between the molecules. The electroluminescence device with the compound as a luminescent layer material has a long service life. According to the nitrogen-containing compound provided by the present disclosure with an indolocarbazole structure connecting with a nitrogen-containing group (triazine, pyridine and pyrimidine) and a benzoxazole or benzothiazole group respectively has a high dipole moment, thereby improving the polarity of the material.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: April 4, 2023
    Assignee: SHAANXI LIGHTE OPTOELECTRONICS MATERIAL CO., LTD.
    Inventors: Tiantian Ma, Kongyan Zhang, Xinxuan Li, Yiyi Zheng
  • Patent number: 11616204
    Abstract: An organic electroluminescence device includes a first electrode; an emission layer on the first electrode; and a second electrode on the emission layer, wherein the emission layer comprises an organometallic compound represented by Formula 1, and the organic electroluminescence device can achieve long life and deep blue light emission:
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: March 28, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Haejin Kim, Soo-Byung Ko, Sungbum Kim, Eunsoo Ahn, Jaesung Lee, Hyunjung Lee
  • Patent number: 11581219
    Abstract: The present disclosure relates to the field of semiconductor packaging processes, and provides a semiconductor structure and a forming method thereof. The forming method includes: providing a semiconductor substrate, where a surface of the semiconductor substrate is provided with an exposed conductive structure; forming a passivation layer on the surface of the semiconductor substrate and a surface of the exposed conductive structure; etching the passivation layer to form a recess, where a bottom of the recess exposes one end of the conductive structure; forming an adhesion layer on a surface of the recess; and etching to form a hole in the bottom of the recess.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: February 14, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Chih-Wei Chang
  • Patent number: 11569088
    Abstract: Methods of enhancing selective deposition are described. In some embodiments, a passivation layer is deposited on a metal surface before deposition of a dielectric material. A block I molecule is deposited on a metal surface, and a block II molecule is reacted with the block I molecule to form a passivation layer.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: January 31, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Yong Wang, Andrea Leoncini, Doreen Wei Ying Yong, John Sudijono
  • Patent number: 11569183
    Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: January 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yu Kuo, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Yi-Yang Lei, Wei-Jie Huang
  • Patent number: 11557734
    Abstract: An organic electroluminescence device includes a first electrode, a second electrode, and an emission layer disposed between the first electrode and the second electrode, wherein the emission layer includes a polycyclic compound having a fused ring system and represented by Formula 1 to achieve high efficiency and improved efficiency drop characteristics in an emission wavelength range:
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: January 17, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ryuhei Furue, Hirokazu Kuwabara
  • Patent number: 11545579
    Abstract: Many of the physical properties of a silicon semiconductor have already been understood, whereas many of the physical properties of an oxide semiconductor have been still unclear. In particular, an adverse effect of an impurity on an oxide semiconductor has been still unclear. In view of the above, a structure is disclosed in which an impurity that influences electrical characteristics of a semiconductor device including an oxide semiconductor layer is prevented or is eliminated. A semiconductor device which includes a gate electrode, an oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer and in which the nitrogen concentration in the oxide semiconductor layer is 1×1020 atoms/cm3 or less is provided.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: January 3, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Tetsunori Maruyama, Yuki Imoto
  • Patent number: 11532649
    Abstract: Provided is a display device including: a capacitor having a first electrode, a first insulating film over the first electrode, and a second electrode over the first insulating film; and a first transistor over the capacitor. The first transistor includes the second electrode a second insulating film over the second electrode, an oxide semiconductor film over the second insulating film, and a first source electrode and a first drain electrode over the oxide semiconductor film. The first source electrode and the first drain electrode are electrically connected to the oxide semiconductor film.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: December 20, 2022
    Assignee: Japan Display Inc.
    Inventors: Tetsuo Morita, Hiroyuki Kimura, Makoto Shibusawa, Hiroshi Tabatake, Yasuhiro Ogawa
  • Patent number: 11527728
    Abstract: The present disclosure relates to organic electroluminescent compounds, and a host material, an electron buffer material, an electron transport material and an organic electroluminescent device comprising the same. By using the organic electroluminescent compounds of the present disclosure, the organic electroluminescent device secures fast electron current properties by intermolecular stacking and interaction, and thus, it is possible to provide the organic electroluminescent device having low driving voltage and/or excellent luminous efficiency and/or efficient lifespan properties.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: December 13, 2022
    Inventor: Hee-Choon Ahn
  • Patent number: 11527726
    Abstract: An organic electroluminescence device including a first electrode, a second electrode, and an emission layer between the first electrode and the second electrode, wherein the emission layer includes a compound represented by Formula 1 to achieve high efficiency and an improved efficiency drop in a deep blue emission wavelength region:
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: December 13, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ryuhei Furue, Hirokazu Kuwabara, Nobutaka Akashi
  • Patent number: 11522147
    Abstract: The present application discloses an organic light-emitting device and a display device, which include a light-emitting layer. The light-emitting layer includes a donor light-emitting layer and an acceptor light-emitting layer, wherein at least one film layer of the donor light-emitting layer and the acceptor light-emitting layer adopts a thermally activated delayed material.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: December 6, 2022
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Fang Wang
  • Patent number: 11521894
    Abstract: Contact designs for semiconductor FET devices are provided. In one aspect, a contact structure includes: a metal line(s); a first ILD surrounding the metal line(s), wherein a top surface of the first ILD is recessed below a top surface of the metal line(s); a liner disposed on the first ILD and on portions of the metal line(s); a top contact(s) disposed over, and in direct contact with, the metal line(s), wherein an upper portion of the top contact(s) has a width W1 and a height H1, wherein a lower portion of the top contact(s) has a width W2 and a height H2, and wherein W1<W2 and H1>H2; and a second ILD disposed over the liner and surrounding the top contact(s). A semiconductor FET device and methods for fabrication thereof are also provided.
    Type: Grant
    Filed: July 18, 2020
    Date of Patent: December 6, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Julien Frougier, Ekmini Anuja De Silva, Eric Miller
  • Patent number: 11515198
    Abstract: Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with dielectric material comprising silicon, oxygen and carbon. The carbon is present to a concentration within a range of from about 3 atomic percent to about 20 atomic percent. Some embodiments include a method of providing dielectric fill across a semiconductor construction having an opening extending therein. The semiconductor construction has an upper surface proximate the opening. The method includes forming photopatternable dielectric material within the opening and across the upper surface, and exposing the photopatternable dielectric material to patterned actinic radiation.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: November 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Scott L. Light, John A. Smythe, Sony Varghese
  • Patent number: 11456286
    Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: September 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Chan Yoo, Todd O. Bolken