Patents Examined by Colleen E Snow
  • Patent number: 11450837
    Abstract: A display device includes: a substrate including a display area, a first non-display area, a second non-display area, and a bending area; a display element disposed on a surface of the substrate; a resin layer disposed on another surface of the substrate to correspond to the display area, where the resin layer exposes at least a portion of the another surface; an external light-absorbing layer disposed on the another surface exposed by the resin layer; and a first protective layer disposed on the another surface of the substrate to correspond to the first non-display area.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: September 20, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ungsoo Lee, Seungwook Kwon, Kibeom Lee, Sooyoun Kim, Wooyong Sung, Seoyeon Lee, Hyoungsub Lee, Moonwon Chang
  • Patent number: 11437299
    Abstract: A semiconductor apparatus comprising a first substrate that has a first surface and a second surface and is provided with a through hole extending through from the first surface to the second surface and an insulating layer and a conductive member that are provided in the through hole is provided. The through hole includes a first opening formed in the first substrate and a second opening provided between the first opening and the second surface. The first opening and the second opening each have a tapered shape whose opening width decreases from the first surface to the second surface, and a first taper angle formed by a side surface of the first opening and a plane parallel to the second surface is smaller than a second taper angle formed by a side surface of the second opening and a plane parallel to the second surface.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: September 6, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Tatsuya Saito
  • Patent number: 11437580
    Abstract: A polymer comprising wherein Ar1 and Ar2 are optional and either the same or different and independently selected from an aryl group or an heteroaryl group. In this polymer, W is selected from the group consisting of: S, Se, O, and N-Q; and Q is selected from the group consisting of: a straight-chain or branched carbyl, silyl, or hydrocarbyl, a branched or cyclic alkyl with 1 to 30 atoms, a fused substituted aromatic ring, and a fused unsubstituted aromatic ring. Additionally, in the polymer, R4 and R5 are selected from the group consisting of: a straight-chain or branched carbyl, silyl, or hydrocarbyl, a branched or cyclic alkyl with 1 to 30 atoms, a fused substituted aromatic ring, and a fused unsubstituted aromatic ring; and x+y=1.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: September 6, 2022
    Assignee: Phillips 66 Company
    Inventors: Hualong Pan, Kathy Woody
  • Patent number: 11424157
    Abstract: A method of manufacturing a structure that includes a substrate provided with a through hole, and a resin layer provided on a front surface of the substrate to close the through hole, includes, in order, preparing the substrate including the through hole and including a support substrate on a back surface of the substrate to close the through hole, bonding a dry film to a front surface of the substrate, the dry film including a support member and a resin layer on the support member, to close the through hole with the resin layer and turn the through hole into a closed space with the substrate, the support substrate, and the dry film, opening the through hole turned into the closed space from the support substrate side, and separating the support member from the dry film while retaining the resin layer on the front surface of the substrate.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: August 23, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Seiichiro Yaginuma, Ryotaro Murakami, Hideomi Kumano, Masahisa Watanabe, Tetsushi Ishikawa
  • Patent number: 11417650
    Abstract: An integrated circuit including a substrate, a first semiconductor element, and a second semiconductor element is provided. The substrate has a high voltage region and a low voltage region separated from each other. The first semiconductor element is located in the high voltage region. The first semiconductor element includes a first oxide layer and a first gate. The first oxide layer is embedded in the substrate. The first gate is located on the first oxide layer. The first gate is a polycrystalline gate. The second semiconductor element is located in the low voltage region. The second semiconductor element includes a second oxide layer and a second gate. The second oxide layer is embedded in the substrate. The second gate is located on the second oxide layer. The second gate is a metal gate. A manufacturing method of an integrated circuit is also provided.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: August 16, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Chieh Pu, Jih-Wen Chou, Chih-Chung Tai
  • Patent number: 11411086
    Abstract: An integrated chip includes a field plate overlying an isolation structure. A gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an upper surface of the gate electrode to a front-side of the substrate. The etch stop layer overlies a drift region disposed between the source region and the drain region. The field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate extends from a top surface of the first ILD layer to an upper surface of the etch stop layer. The isolation structure is disposed within the substrate and extends from the front-side of the substrate to a point below the front-side of the substrate. The isolation structure is disposed laterally between the gate electrode and the drain region.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: August 9, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kaochao Chen, Chia-Cheng Ho, Ming Chyi Liu
  • Patent number: 11410881
    Abstract: Methods of forming copper interconnects are described. A doped tantalum nitride layer formed on a copper layer on a substrate has a first amount of dopant. The doped tantalum nitride layer is exposed to a plasma comprising one or more of helium or neon to form a treated doped tantalum nitride layer with a decreased amount of dopant. Apparatus for performing the methods are also described.
    Type: Grant
    Filed: June 28, 2020
    Date of Patent: August 9, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Rui Li, Xiangjin Xie, Tae Hong Ha, Xianmin Tang, Lu Chen
  • Patent number: 11404462
    Abstract: Image quality of an imaging element having a configuration in which pixels having color filters are arranged two-dimensionally is prevented from being lowered. An imaging element includes a plurality of pixels and incident light attenuation sections. The pixel includes a color filter transmitting incident light having a predetermined wavelength, and a photoelectric conversion section that produces an electric charge according to the light transmitted through the color filter. The incident light attenuation section is disposed between the color filters of the adjacent pixels, is configured to be different in surface height from the color filters, and attenuates light not transmitted through the color filter but incident on the photoelectric conversion section of the pixel where the color filter is disposed.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: August 2, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yuichi Seki, Yoichi Ootsuka
  • Patent number: 11387139
    Abstract: A method of manufacturing a semiconductor device, the method including: a first film deposition process of stacking a polymer film on a substrate on which a recess is formed, wherein the polymer film is a film of a polymer having a urea bond and is formed by polymerizing a plurality of kinds of monomers; a second film deposition process of stacking a sealing film on the substrate in a state in which at least a bottom and a sidewall of the recess are covered with the polymer film; and a desorbing process of desorbing and diffusing the polymer film under the sealing film through the sealing film by depolymerizing the polymer film by heating the substrate to a first temperature.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: July 12, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Syuji Nozawa, Tatsuya Yamaguchi, Sunghil Lee
  • Patent number: 11355635
    Abstract: A semiconductor structure includes a substrate, a first semiconductor fin, a second semiconductor fin, and a first lightly-doped drain (LDD) region. The first semiconductor fin is disposed on the substrate. The first semiconductor fin has a top surface and sidewalls. The second semiconductor fin is disposed on the substrate. The first semiconductor fin and the second semiconductor fin are separated from each other at a nanoscale distance. The first lightly-doped drain (LDD) region is disposed at least in the top surface and the sidewalls of the first semiconductor fin.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung Tsai, Kuo-Feng Yu, Kei-Wei Chen
  • Patent number: 11355724
    Abstract: An organic light-emitting diode (OLED) structure includes a stack of OLED layers; a light extraction layer (LEL) comprising a UV-cured ink; and a UV blocking layer between the LEL and the stack of OLED layers.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: June 7, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Gang Yu, Chung-Chia Chen, Wan-Yu Lin, Hyunsung Bang, Lisong Xu, Byung Sung Kwak, Robert Jan Visser
  • Patent number: 11335625
    Abstract: A via hole structure includes: a first conductive layer, an interlayer insulating layer, and a second conductive layer that are sequentially arranged, wherein the interlayer insulating layer is provided with a via hole, the second conductive layer is overlapped with the first conductive layer by the via hole, and at least part of a surface, in contact with the second conductive layer, of the interlayer insulating layer is uneven.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: May 17, 2022
    Assignees: Mianyang BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Lei Zhang, Daqing Sun, Wei Qiu, Fangliang Yan
  • Patent number: 11329134
    Abstract: A method for manufacturing a semiconductor device according to an embodiment includes: forming a first silicon oxide film on a surface of a silicon carbide layer; and performing first heat treatment at 1200° C. or more in an atmosphere including nitrogen gas and carbon dioxide gas.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: May 10, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo Shimizu
  • Patent number: 11322701
    Abstract: A high dielectric constant composite material and method for preparing organic thin film transistor using the material as dielectric. The method includes: using sol-gel method, hydrolyzing terminal group-containing silane coupling agent to form functional terminal group-containing silica sol, cross-linked with organic polymer to form composite sol as material of dielectric of organic thin film transistor; forming film by solution method such as spin coating, dip coating, inkjet printing, 3D printing, etc., forming dielectric after curing; preparing semiconductor and electrode respectively to prepare organic thin film transistor device, which, based on composite dielectric material, has mobility of 5 cm2/V·s, exceeding that of using SiO2, having low threshold voltage and no hysteresis effect. Compared with traditional processes like SiO2 thermal oxidation, above method has advantages of simple process, low cost, suitable for large-area preparation, with great market application value.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: May 3, 2022
    Assignee: PEKING UNIVERSITY SHENZHEN GRADUATE SCHOOL
    Inventors: Hong Meng, Jupeng Cao, Lijia Yan, Yu He, Xiaoyun Wei, Yanan Zhu, Ting Li
  • Patent number: 11322391
    Abstract: Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tz-Jun Kuo, Chien-Hsin Ho, Ming-Han Lee
  • Patent number: 11316109
    Abstract: The present invention discloses a patterned perovskite film, a preparation method thereof, and a display device. The method includes mixing a perovskite precursor and a photo-initiated polymer monomer, and realizing polymerization of a part of a predetermined area under shielding of a photomask, that is, the formed perovskite crystals are encapsulated by the formed polymer with formation of the patterned perovskite film.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: April 26, 2022
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Zhiping Hu
  • Patent number: 11316114
    Abstract: The present invention relates to an organic EL device comprising an electron buffer material, and a first electrode, a second electrode opposing the first electrode, a light-emitting layer disposed between the two electrodes, and an electron transport zone and an electron buffer layer disposed between the light-emitting layer and the second electrode. By using an electron buffer material according to the present invention, the organic EL device having low driving voltage, high luminous efficiency, and excellent lifespan can be provided.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: April 26, 2022
    Assignees: DOW GLOBAL TECHNOLOGIES LLC
    Inventors: Sang Hee Cho, Hong Yeop Na, Zhengming Tang, Shaoguang Feng, Doo-Hyeon Moon
  • Patent number: 11302896
    Abstract: A display panel and a manufacturing method thereof, and a display device are provided. The display panel includes a substrate and a display layer disposed on the substrate. Furthermore, a thin-film encapsulation structure is disposed on the display layer. The thin-film encapsulation structure includes a first barrier layer and a first buffer layer which are disposed sequentially, and two lateral sections of the first barrier layer and the first buffer layer disposed on the first barrier layer are respectively packaged by a first lateral sectional barrier layer. A width of the first barrier layer and a width of the first buffer layer are equal.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: April 12, 2022
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Chao He
  • Patent number: 11296296
    Abstract: An organic light-emitting diode (OLED) structure includes a stack of OLED layers that includes a light emission zone having a planar portion, and a light extraction layer formed of a UV-cured ink disposed over the light emission zone of the stack of OLED layers. The light extraction layer has a gradient in index of refraction along an axis normal to the planar portion.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: April 5, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Gang Yu, Chung-Chia Chen, Wan-Yu Lin, Hyunsung Bang, Lisong Xu, Byung Sung Kwak, Robert Jan Visser
  • Patent number: 11296127
    Abstract: The present disclosure provides a display substrate, a method for manufacturing the same and a display device. The display substrate includes a base substrate, first wires on a side of the base substrate, a first barrier layer on the side of the base substrate; and a second wire on a side of the first barrier layer distal to the base substrate, where the first wires and the second wire being adjacent to and spaced apart from each other.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: April 5, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jing Wang, Dong Li, Xiaodong Xie, Min He, Weiwei Chu, Wenjie Xu, Yuan Li, Yaying Li