Abstract: A computer network connects information providers and end-users of network services, facilitates direct information to users, and gathers user responses. The computer network is designed to use otherwise idle bandwidth of the network transmission medium to transfer targeted commercial and non-commercial information to users while minimizing the delay of normal network traffic. User reports containing demographics and user responses are generated ensuring user privacy. Information providers can access user reports without violating user anonymity.

Abstract: Within a computing system, the main memory is segmented in order to streamline data paths for data transactions between input/output devices. The computing system includes both a host bus and an input/output bus. One or more processors are connected to the host bus. A bus bridge connects the input/output bus to the host bus. The bus bridge is used for transferring information between the host bus and the input/output bus. The main memory for the computing system is segmented as follows. A first main memory segment is connected to the host bus. A second main memory segment is connected to the input/output bus. The first main memory segment and the second main memory segment are configured to appear to the processors as a single logical memory image. The segmented main memory is used to streamline data paths for the computing system.

Abstract: A disk drive has two channels of upper interfaces, and one channel is connected to a disk array controller, and the other channel is connected between a plurality of disk drives. A data disk drive reads the old data on the recording medium, calculates the exclusive OR of the old data and the corresponding data from the disk array controller, and transfers it to a parity disk as pseudo-parity data from the other channel. The parity disk drive reads the old parity data on the recording medium, calculates the exclusive OR of the old parity data and the pseudo-parity data, and writes it as new parity data.

Abstract: A dependency checking structure is provided which compares memory accesses performed from the execution stage of the instruction processing pipeline to memory accesses performed from the decode stage. The decode stage performs memory accesses to a stack cache, while the execution stage performs its accesses (address for which are formed via indirect addressing) to the stack cache and to a data cache. If a read memory access performed by the execution stage is dependent upon a write memory access performed by the decode stage, the read memory access is stalled until the write memory access completes. If a read memory access performed by the decode stage is dependent upon a write memory access performed by the execution stage, then the instruction associated with the read memory access and subsequent instructions are flushed. Data coherency is maintained between the pair of caches while allowing stack-relative accesses to be performed from the decode stage.

Abstract: In a computer system a plurality of workstations are connected to each other by a network. Each workstation including a processor, a memory having addresses, and an input/output interface connected to each other by a bus. The input/output interfaces connect the workstations to each other via the network. Valid data accesses are checked by a software implemented method. A set of the addresses of the memories are designated as virtual shared addresses to store shared data. A particular one of the programs allocates a portion of the virtual shared addresses to store a shared data structure as one or more blocks accessible by the programs executing in any of the processors. The size of a particular block depends on the size of the shared data structure. Each block including an integer number of lines, each line including a predetermined number of bytes. The program is instrumented to initialize the bytes allocated for the shared data structure to a predetermined flag value.

Abstract: An interleaved cache memory having a single-cycle multi-access capability is disclosed. The interleaved cache memory comprises multiple subarrays of memory cells, an arbitration logic circuit for receiving multiple input addresses to those subarrays, and an address input circuit for applying the multiple input addresses to these subarrays. Each of these subarrays includes an even data section and an odd data section and three content-addressable memories to receive the multiple input addresses for comparison with tags stored in these three content-addressable memories. The first one of the three content-addressable memories is associated with the even data section and the second one of the three content-addressable memories is associated with the odd data section. The arbitration logic circuit is then utilized to select one of the multiple input addresses to proceed if more than one input address attempts to access the same data section of the same subarray.

Abstract: A computer system has a host system and a disk drive external thereto. In order to adapt the disk drive to interchangeable use with two or more different types of disks such as double density disks and high density disks of both 1.25 and 1.44 megabyte capacities, the host system first determines which of the interchangeable types of disks is loaded in the disk drive. If a different operating mode such as a different disk speed proves necessary in the disk drive, the host produces a selected one of standard disk drive control signals in combination with a mode change command for multiplex transmission to the disk drive. No dedicated channel is therefore needed for sending the mode change command from the host to the disk drive. Stepping pulses are utilized in one embodiment for carrying the mode change command, in the form of consecutive stepping pulses, the number of which is greater than that required for moving the head across all the tracks on any of the interchangeable disks.

Abstract: A dynamic memory refresh apparatus includes a programmable refresh interval generator that generates an interval for generating a refresh request signal. The refresh interval time is based on the manufacturer specified DRAM cycle time, the system clock period, and the number of memory segments on the memory board that are supported by the computer system. The refresh interval time substantially maximizes the time between refreshes of a particular DRAM module. The dynamic refresh apparatus also includes a memory segment pointer generator that generates a memory segment pointer. The memory segment pointer points to the next memory segment to be refreshed. The memory segment pointer is generated such that the memory segments are selected in a staggered manner. In addition, the dynamic memory refresh apparatus includes a refresh request generator that generates a refresh request signal for the memory segment pointed to by the memory segment pointer.

Abstract: In a computer system having a hierarchical memory, the problem of tolerating cache miss latency is solved by dynamically switching appropriately between two different code sequences, one optimized at compile-time, assuming a cache-hit, and the other optimized at compile-time, assuming a cache-miss.

Abstract: A control device is provided that controls a connection between a specific one of a plurality of arithmetic processors and a specific one of a plurality of main memory units in accordance with an access request supplied from the specific arithmetic processor. The access request has request tag information. A buffer section buffers the request tag information in response to a write-in address. A supplying section supplies the specific main memory unit with an additional access request having the write-in address as an identifier instead of the request tag information. When the specific main memory access ends, the specific memory unit supplies the control device with a reply signal having the identifier as a reply identifier. A read section reads the request tag information out of the buffer section in accordance with the reply identifier. The request tag information is delivered from the control device to the specific arithmetic processor.

Abstract: An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by the latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for external output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputers, large size calculators, work stations and personal computers can be improved.

Abstract: A hierarchical memory utilizes a translation lookaside buffer for rapid recovery of virtual to real address mappings and a cache system. Lines in the cache are identified in the cache directory by pointers to entries in the translation lookaside buffer. This eliminates redundant listings of the virtual and real addresses for the cache line from the cache directory allowing the directory to be small in size. Upon a memory access by a processing unit, a cache hash address is generated to access a translation lookaside buffer entry allowing comparison of the address stored in the TLB entry with the address of the memory access. Congruence implies a hit. Concurrently, the cache hash address indicates a pointer from the cache directory. The pointer should correspond to the cache hash address to indicate a cache directory hit. Where both occur a cache hit has occurred.

Abstract: A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined, fixed set of instructions, combined with one or more programmable execution units coupled to the internal buses for execution of a set of program instructions, to provide an on chip reprogrammable instruction set accelerator RISA. Reprogrammable execution units may be made using field programmable gate array technology having configuration stores. Techniques for translating a computer program into executable code relying on the RISA involve providing a library of defined and programmed instructions, and compiling a program using the library to produce an executable version of the program using both defined and programmed instructions. The executable version can be optimized to conserve configuration resources for the programmable execution unit, or to optimize speed of execution.

Abstract: A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined, fixed set of instructions, combined with one or more programmable execution units coupled to the internal buses for execution of a programmed instruction providing an on chip reprogrammable instruction set accelerator RISA. The programmable execution units may be made using a field programmable gate array having a configuration store, and resources for accessing the configuration store to program the programmable execution unit. An instruction register is included in the data processor which holds a current instruction for execution, and is coupled to an instruction data path to supply the instruction to the defined instruction unit and to the programmable instruction units in parallel, through appropriate decoding resources. A RISA instruction page table is used to detect when an instruction in the sequence has not been configured for the RISAs on chip.

Abstract: A field programmable gate array (FPGA) memory system which allows the same array of memory to contain both configurable memory and user memory. The FPGA user logic can modify the information contained within the configurable memory and the user memory. The information stored within the configuration memory defines the logic within the user logic. Therefore, the user logic can modify sections of the logic within the user logic. The configuration memory and the user memory share resources such as address decoders, bitlines and sense amplifiers.

Abstract: A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined set of instructions, combined with a programmable execution unit coupled to the internal buses for execution of a programmed instruction providing an on chip reprogrammable instruction set accelerator RISA. The programmable execution unit may be made using a field programmable gate array having a configuration store, and resources for accessing the configuration store to program the programmable execution unit. An instruction register is included in the data processor which holds a current instruction for execution, and is coupled to an instruction data path to supply the instruction to the defined instruction unit and to the programmable instruction unit in parallel, through appropriate decoding resources.

Abstract: At a predetermined time before activation of a motor of a hard disk drive HDD, a central processing unit CPU transfers a part of a speed control routine or a part of a position control routine from a read only memory ROM via an external bus, and stores the transferred part in a command random access memory RAM. When a servo process is executed, the CPU accesses to the ROM and the command RAM and executes a head positioning control consisting of a speed control and a position control. Thereby, a routine stored in the command RAM can be accessed at high speed. As a result, a servo process time period can be reduced.

Abstract: A computer system is disclosed including a memory subsystem and a processor subsystem having an external cache and an external mechanism for invalidating cached datablocks in the processor subsystem and for reducing false invalidation operations. The processor subsystem issues a write invalidate message to the memory subsystem that specifies a datablock and that includes an invalidate advisory indication that indicates whether the datablock is present in the external cache. The invalidate advisory indication determines whether the memory subsystem returns an invalidate message to the processor subsystem for the write invalidate operation.

Abstract: A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU includes a target cache organized in banks to support split prefetching. Prefetch requests (addressing a prefetch block of 16 bytes) are separated into low and high block addresses (addressing split blocks of 8 bytes). The low and high block addresses differ in bit position ?3! designated a bank select bit, where the low block address of an associated prefetch request may be designated by a ?1 or 0! such that a split block associated with a low block address may be allocated into either bank of the target cache (i.e., the low block of a prefetch request can start on an 8 byte alignment rather than the 16 byte alignment).

Abstract: Referring to FIGS. 1, 4, and 5, I/O control modules (IOCMs 25-29) include pin/status buses (75-77) which allow the transfer of pin information between integrated circuit pins (31-35) and one or more channels in IOCMs (25-29). In one embodiment, a pins/status bus (e.g. 76) may be programmably configured to permit the logical combination of the outputs of multiple channels (e.g. 160, 161, 185) in order to determine the logic state of an output pin (165). In one embodiment, the output event bus portion (e.g. 132) of a pin/status bus (e.g. 76) includes one or more set conductors (137), one or more clear conductors (138), and one or more toggle conductors (139), which may be wire-NOR conductors.