Abstract: A semiconductor disk device includes an interface that connects to a host unit operating under DOS; a flash memory having at least one continuous data storage area for storing data; a control circuit that controls data input/output with the host unit through the interface and that manages addresses of the main memory, and a cache memory connected to the control circuit and accessible to the main memory through the control circuit. Data files supplied from the host unit are written in the data storage area beginning at the lowest available address and a directory entry file associated with a data file is written into the data storage area immediately following and contiguous to the data file. Additional data and directory entry files are similarly stored sequentially.

Abstract: A FIFO with locked exchange capability is disclosed. The FIFO has a memory for storing and retrieving data submissions, a write address generator and a read address generator for sequentially addressing the memory. A difference counter maintains the difference between the number of writes to the queue and reads from the queue. The net difference, as tracked by the counter is a measure of the FIFO utilization. To detect the queue full condition, a comparator compares the maximum FIFO stack depth against the counter output. The result of this comparison is latched and provided to a write strobe generator so that, in a subsequent write operation, if the FIFO is full, the write strobe from the producer is blocked and the data will not be written to the FIFO. Otherwise, the write strobe from the producer is passed to the memory. Additionally, a remaining space count is maintained in a status register.

Abstract: A register file including multiple register storages and multiple read ports is provided. Each register storage stores a subset of the architected register set for the microprocessor within which the register file is employed. Each register storage is coupled to select ones of the multiple read ports, reducing wiring and complexity of the register file. Each read port is coupled to a subset of the registers within the register file. The subset of the registers to which the read port is coupled is defined by the register storage(s) to which the read port is coupled. Access to a particular register is thereby restricted to a subset of the read ports coupled to the register file. However, for data access patterns such as the data access patterns characteristic of DSP functions, such restrictions may have an insignificant impact upon performance.

Abstract: A method is disclosed for publishing a hypertext file set on a world-wide web server machine by packaging the hypertext file set as an e-mail message on a client machine, transporting the e-mail message over the internet from the client machine to the world-wide web server machine, unpacking the e-mail message to recover the hypertext file set, and depositing the hypertext file set into a memory means on the world-wide web server machine. By using the e-mail transport mechanism, a direct internet connection between the client and server is not necessary. Consequently, the method allows files to pass through security firewalls and allows geographically disperse individuals to remotely update information at a WWW site without compromising server security. In addition, processing time is not wasted during direct connections sharing the server's resources and internet bandwidth is not wasted.

Abstract: An IC (integrated circuit) memory is made by using a chip of a minimum size that can accommodate memory of a desired capacity. Specifically, the chip has the size of (6.33.times.6.34) mm.sup.2, and its effective chip size is (4.33.times.4.43) mm.sup.2 1-port RAM (random access memory) 1 of 792w (word length).times.24 bits (bit width), 1-port RAM 2 of 220w.times.24 bits, and a logic circuit having about 3,000 gates for controlling these RAMs are provided in the effective chip size.

Abstract: A random access memory (RAM) device that allocates memory cells to first-in first-out (FIFO) memory. The RAM device has an array of addressable memory cells that are selected by row and column decoders. The memory cells and decoders have dual read and write lines that allow simultaneous read and write operations on the memory cells. The memory cells can store data from at least two data streams including, by way of example, a stream of U data and a stream of V data from an input device such as a YUV video processor. The RAM device includes a control circuit which generates separate read and write pointers for the U and V data. The control circuit also generates separate U and V minimum and almost full trigger pointers. Data is written into the memory cells until a write pointer reaches either a minimum trigger pointer or an almost full trigger pointer.

Abstract: For an synchronous dynamic access memory ("S-DRAM") system including a memory assembly with multiple memory units, data access commands are placed on a command bus at specific times to facilitate gapless data bus operation. After receipt of a first memory access request, a first memory access command is issued on the command bus to exchange a first data string having a first length with a first one of the memory units. Subsequently, receipt occurs of a second memory access request is to exchange a second data string, of a second length, with a second one of the memory units. A determination is made of an earliest possible time for placement of a second memory access command upon the command bus; this considers various factors, such as the first length, data bus availability, command bus availability, and any predetermined delay in placement of the first data string onto the data bus. Accordingly, the second memory access command is placed upon the command bus at the determined time.

Abstract: A computer memory device has a predetermined number of individually addressable storage cells and an internal addressing mechanism for storing a full address that determines which of the predetermined number of individually addressable storage cells will be accessed during a next memory access operation. The internal addressing mechanism includes a number of address segment registers whose concatenated outputs represent the full address. The width of each of the address segment registers is equal to the size of the address bus that couples the memory device to a processor. Mode control signals, sent by the processor, instruct the memory device to load a particular one of the address segment registers, thereby eliminating the need to include a number of address pins equal to the number of bits in the full address.

Abstract: A method and apparatus for improving performance of bit block transfers in display controllers during clipping functions without significantly increasing gate count. In a clipping function, particularly when transferring a portion of a monochrome bit map and color expanding same or in pattern copying, a source start address may not lie on a byte boundary. In order to avoid using time consuming shift left operations in software, the source start address may be adjusted in hardware to an earlier byte boundary. Upon writing data to a destination address, a hardware byte mask may be employed to prevent writing of the additional data retrieved due to the adjustment of the source start address. The source start address and byte mask hardware may be implemented in hardware using bit block transfer engine components and a small amount of additional hardware. The remainder of the clipping functions may remain in software, for example in a display device driver.

Abstract: A memory subsystem includes a posted write buffer for dynamic random access memories (DRAMs). The posted write buffer includes read around logic to enable read accesses to be processed in advance of posted writes. Data are transferred from the posted write buffer to the DRAMs on a general first-in/first out basis; however, in order to take advantage of page mode operation, posted writes having the same row address as a current memory access are given priority over other posted writes such that the posted writes may be written out of order. In addition, comparisons are made between addresses of incoming read accesses and addresses of posted writes in order to expedite the transfer of posted writes having the same row addresses to memory in order to service the incoming read accesses on a timely basis. An improved write access buffer permits posted writes to be transferred to the DRAMs out of order without losing track of the skipped posted writes.

Abstract: Within a computing system, the main memory is segmented in order to streamline data paths for data transactions between input/output devices. The computing system includes both a host bus and an input/output bus. One or more processors are connected to the host bus. A bus bridge connects the input/output bus to the host bus. The bus bridge is used for transferring information between the host bus and the input/output bus. The main memory for the computing system is segmented as follows. A first main memory segment is connected to the host bus. A second main memory segment is connected to the input/output bus. The first main memory segment and the second main memory segment are configured to appear to the processors as a single logical memory image. The segmented main memory is used to streamline data paths for the computing system.

Abstract: A method and apparatus for snooping both cache memory and associated buffer queues in a cache subsystem arrangement. Since there are usually several requests for cache data being handled at any given time under high performance operation of multiple processors, a cache arrangement includes at least one buffer queue for storing the address of the cache data line and the status of the cache data line, which facilitate keeping track of the data requests and handling them efficiently. In response to a snoop request, a snoop address is compared to the address stored in the buffer queue so as to provide a positive comparison result if the snoop address matches the address stored in the buffer queue, thereby indicating a snoop hit condition. The buffer queue of the cache arrangement further has a snoop hit bit for storing a record of the positive comparison result that indicates the snoop hit condition.

Abstract: The present invention encompasses techniques for reducing digital noise in integrated circuits and circuit assemblies, particularly dense mixed-signal integrated circuits, based upon shaping the noise from the digital circuit and concentrating it in a single, or a small number, of parts of the frequency spectrum. Generally, the presence of noise in the analog circuit is less important at certain frequencies, and therefore the spectral peak or peaks from the digital circuit can be carefully placed to result in little or no interference. As an example, a radio receiver might be designed such that the peaks of the digital noise lie between received channels, outside the band edges of each.

Abstract: A memory subsystem includes a posted write buffer for dynamic random access memories (DRAMs). The posted write buffer includes read around logic to enable read accesses to be processed in advance of posted writes. Data are transferred from the posted write buffer to the DRAMs on a general first-in/first out basis; however, in order to take advantage of page mode operation, posted writes having the same row address as a current memory access are given priority over other posted writes such that the posted writes may be written out of order. In addition, comparisons are made between addresses of incoming read accesses and addresses of posted writes in order to expedite the transfer of posted writes having the same row addresses to memory in order to service the incoming read accesses on a timely basis. An improved write access buffer permits posted writes to be transferred to the DRAMs out of order without losing track of the skipped posted writes.

Abstract: Computer systems using a processor that is capable of operating in a system management mode (SMM) employ a dedicated system management RAM (SMRAM). The processor uses the SMRAM when the processor is performing a task associated with the SMM. The processor is capable of generating a range of system addresses. The range includes a particular subrange of system addresses that are used for accessing the SMRAM. A memory controller decodes the system addresses generated by the processor and enables access to the SMRAM, regardless of whether the processor is operating in the SMM, when the controller decodes a system address of the particular subrange. The range of system addresses also includes a second subrange. The memory controller also enables access to the SMRAM when the processor is operating in the SMM and the controller decodes a system address of the second subrange. The memory controller indicates to the processor whether data associated with the enabled SMRAM can be stored in a cache memory.

Abstract: An improved storage device repair mechanism is provided. The storage device repair mechanism of the preferred embodiment searches the storage device and detects cross-linked clusters and lost directories. In response to detecting a cross-linked cluster, the repair mechanism of the preferred embodiment duplicates the cross-linked cluster and attaches the cross-linked cluster to one of the cross-linked cluster chains. In response to detecting a lost directory, the repair mechanism of the preferred embodiment attaches the lost directory to the root directory.

Abstract: A distributed processing system includes a plurality of processors connected to a transmission line and adapted to respectively execute assigned processes. Each processor includes a transmission/reception processing section, a memory, a memory management section, and a processing section. The transmission/reception processing section transmits/receives data to/from the remaining processors through the transmission line. The memory is used during execution of a process. The memory management section manages the memory. The memory management section ensures an available area in the memory managed by the memory management section of at least one of the remaining processors through the data transmission/reception processing section when a capacity shortage occurs in the memory at the start of a process, and ensures an available area in the memory instead of the available area in the memory of the remaining processor when the available area occurs in the memory during execution of the process.

Abstract: Both interactively-selectable information and audio information are recorded on a compact disc medium. The music is recorded in Red Book format on the disc in a normal way so that it is reproducible by a standard CD player. The Red Book information is also re-recorded in Yellow Book format in a different area on the disc. The Yellow Book information may be compressed. A second portion of Yellow Book information includes interactively-selectable program information. The music information is not interrupted unless selected by a user.

Abstract: A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface having master classes for sending memory transaction requests to the system controller. The system controller includes memory transaction request logic for processing each memory transaction request by a data processor. The system controller maintains a duplicate cache index having a set of duplicate cache tags (Dtags) for each data processor.

Abstract: An efficient procedure for determining the set of buffer pool database pages that must be externalized to stable storage and for scheduling their write I/O's before release of a committing transaction's locks. In a multisystem database management system (DBMS) with high-speed shared external storage (SES) environment, a DBMS instance may follow "force-at-commit" protocol for a database that has intersystem read/write interest or may alternatively follow a "no-force-at-commit" policy when operating with a database for which only one system has interest. By introducing the concept of a series of unique ordinal numbers (ORD#) for each database assigned to buffer pool data pages whenever the page state changes from clean to dirty within a single DBMS instance, this procedure maintains a transaction page list (TPL) for each transaction in ORD# order.