Abstract: In a semiconductor integrated circuit, a digital circuit section and an analog circuit section are formed on a substrate. A pair of first power source lines connects a circuit element in the digital circuit section to a power source, while a pair of second power source lines connects a substrate region in the digital circuit section to the power source. The pair of second power source lines is formed separately from the pair of first power source lines in the digital circuit section. The substrate region in the digital circuit section is surrounded by a guard ring well, to which one of the pair of second power source lines is connected.

Abstract: vertical power MOSFET which comprises a semiconductive substrate of a first conductivity type serving as drain, an impurity region of a second conductivity type on a part of the surface of the semiconductive substrate, an impurity region of a first conductivity type formed on a part of the surface of the second conductivity type impurity region and serving as source, and a surface portion of a second conductivity type semiconductive substrate between source and drain serving as a channel portion with a gate electrode thereon through an insulating film, so that voltage is applied to the gate electrode to control channel current between source and drain, wherein the first conductivity type semiconductive substrate comprises a low resistivity layer and a high resistivity layer epitaxially formed on the low resistivity layer, and at an interface between the low resistivity layer and the high resistivity layer is provided a convexed portion which projects at least to the high resistivity layer side.

Abstract: A plastic mold semiconductor device comprises a semiconductor chip; a die pad which is made of a thin metallic plate for supporting the semiconductor chip; leads which surround the die pad, wires for connecting electrodes on top of the semiconductor chip and the leads; and plastic mold for sealing the entire device; the die pad being comprised of support sections separated by a fixed gap from a sub-element interconnecting member which is insulated from the semiconductor chip, and connection between the power source or signal related lead and the electrode which is on top the semiconductor chip and is located from the power source or signal related lead is connected by the sub-element interconnecting member.

Abstract: A bridge electrode structure and method of fabrication thereof is provided that is adapted to provide electrically isolated metal bridges over the active portions of a monolithic micromechanical transducer. The bridge electrode of the invention is also adapted to operate in facing relationship with one or more buried electrodes, providing top-to-bottom symmetry for balanced application of forces, or motion detection when used in conjunction with transducer elements. The transducer, typically a gyroscope or an accelerometer, includes a semiconductor substrate and active elements etched out of the substrate, the active elements including flexure-supported transducer plates. The bridge electrodes are anchored at opposing points on the substrate's surface to metal layers used to facilitate their electro-forming. The central portions of the bridge are electroplated over an insulating spacer, such as a photoresist layer.

Abstract: The present invention provides a semiconductor device having a well, formed in a semiconductor substrate by using a mask in which a mask pattern width of a portion corresponding to an opening diameter is equal to or less than twice the diffusion depth of the well layer, and a gate electrode formed to have the well layer as a channel region of a MOS transistor. The well formed in this manner has a substantially semi-circular section to facilitate impurity concentration control in the substrate surface. When a plurality of types of opening patterns having small pattern widths are formed in a single mask, MOS transistors having different threshold voltages can be formed in a single process.

Abstract: An input circuit of a semiconductor device includes a P type well formed on the main surface of a semiconductor substrate, and an N type region formed on the main surface in the P type well. A P-N junction is formed by the N type region and the P type well. An input voltage is applied to the N type region, which input voltage is applied to an internal circuit formed on the semiconductor substrate. When the P-N junction is rendered conductive by an application of an excessive voltage to the input voltage, the current caused by the excessive voltage is absorbed to the supply potential through the P type region formed in the P well.

Abstract: A read-only semiconductor memory device including memory elements arranged in a principal surface of the semiconductor substrate in a matrix to form MOS transistors. Each of the memory elements has first and second electrode regions formed in the principal surface so as to respectively constitute the first and second electrodes, insulative layers formed on the principal surface, and a control electrode layer formed via the insulative layers on the principal surface to constitute the control electrode. The control electrode layer is commonly connected to memory elements in the lateral direction of the matrix. The first and second electrode regions are respectively arranged such that any adjacent two in the vertical direction of the memory elements electrically share the first and second electrodes, respectively. Each of the first electrode regions is interconnected to the first electrode region of one of the elements adjacent thereto in the lateral direction.

Abstract: On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.31 epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer.

Abstract: A MOS transistor includes a gate electrode layer formed on an insulation layer which is formed on an element formation region defined by a field insulation layer formed on a P-type semiconductor substrate. The gate electrode layer has first and second openings formed therein. Further, N-type impurity diffusion regions acting as the drain and source of the MOS transistor are formed in those portions of the surface area of the semiconductor substrate which lie under the first and second openings.

Abstract: A capacitor suitable for use with a DRAM memory cell is composed of multiple layers of polycrystalline silicon. The storage node is formed from a polycrystalline silicon layer sandwiched between two polysilicon ground plate layers. Such a structure nearly doubles the capacitance for a given chip surface area used. First the bottom polycrystalline silicon plate layer is fabricated, followed by an isolation step and fabrication of the storage node polycrystalline silicon layer. Following another isolation step, the polycrystalline silicon top plate layer is then formed and connected to the bottom plate layer.

Abstract: An improved Fermi FET structure with low gate and diffusion capacity allows conduction carriers to flow within the channel at a predetermined depth in the substrate below the gate, without requiring an inversion layer to be created at the surface of the semiconductor. The low capacity Fermi FET is preferably implemented using a Fermi Tub having a predetermined depth, and with a conductivity type opposite the substrate conductivity type and the same conductivity type as the drain and source diffusions.

Abstract: Described is a luminescent semiconductor element having the following structure: a first thick connecting semiconductor layer of uniform material composition, a thin over-graded layer arranged on the first semiconductor layer and comprising connecting semiconductor material whose composition has a linear gradient, a further connecting semiconductor layer arranged on the over-graded layer and having uniform material composition that determines the wavelength of the radiation emitted by the luminescent semiconductor element, an active layer arranged in the surface area of the further semiconductor layer and having a conductivity opposite to that of the further semiconductor layer in order to form a p-n junction, a rear contact arranged on the first connecting semiconductor layer, and a front contact arranged on the surface of the active layer.

Abstract: A design for EPROMs, EEPROMs, and Flash EEPROMs is described which greatly increases the coupling coefficient of the cell and enhances cell access speed. The increase in control gate to floating gate coupling is due to a decrease in the capacitance between the floating gate and the substrate, which includes the drain, source, and channel. This increase in the coupling coefficient will allow for a smaller cell size and better program and erase characteristics. A reduction in the capacitance between the floating gate and the transistor drain will reduce the so-called drain coupling effect. Severe drain coupling could increase undesirable drain-to-source leakage. Finally, a structure comprising the invention has a faster cell access time resulting from the fact that half the cell channel region is directly controlled by the control gate. This half of the channel region will see higher effective vertical electric field from the control gate than the channel region covered by the floating gate.

Abstract: A structure and method of fabricating a active matrix display with halftone grayscale and wide viewing angle, having an active matrix array and a control capacitor array fabricated on separate substrates.

Abstract: At least two unit transistor groups, each including unit transistors arranged along a straight line, are disposed on a substrate parallel to and facing each other. Each transistor in one group and a facing transistor in the other group have integral first, second, and control electrodes. The first, second, and control electrodes of the unit transistors are connected to associated respective electrode pads.

Abstract: An active matrix display includes pixel electrodes (4) which are formed over an insulating layer (17). The insulating layer (17) covers signal lines (2) which supply an image signal and also connect one pixel electrode (4) with another. The insulating layer (17) also covers an additional capacitor common line (8). The pixel electrodes (4) at least partially overlay the signal lines (2) and the additional capacitor common line (8), thereby achieving a larger numerical aperture for the display.

Abstract: An MOS FET of the semiconductor device includes a semiconductor substrate on which a projection is formed via a given film. The projection is made of a polysilicon having grain boundaries. A pair of gate electrodes are provided so that one of the gate electrodes faces the other thereof via side walls of the projection and gate oxide films. A conductive channel forming area is formed at the side walls of the projection, so that the extending direction of the channel is parallel to the thickness direction of the substrate.

Abstract: A method for fabricating a plurality of semiconductor photodetectors and an array of same produced by the method. The method includes a first step of selectively removing semiconductor material to form a channel within a semiconductor material for physically isolating a first photodetector from a second photodetector, the semiconductor material having a characteristic energy bandgap. The method includes a second step of selectively increasing the carrier concentration of the semiconductor material within a bottom region of the channel for preventing minority charge carriers from diffusing under the channel from a region associated with the first photodetector to a region associated with the second photodetector. The step of selectively removing is accomplished by the steps of providing a patterned mask upon the semiconductor material and selectively removing the underlying semiconductor material through an opening within the mask.

Abstract: A capacitor of a semiconductor memory device includes a planar type capacitor portion formed on a surface of an impurity region and a stacked type capacitor portion extending above the gate electrode. The stacked capacitor portion has a three-layer structure of polycrystalline silicon in which upper, lower and side surfaces of a lower electrode are surrounded by a dielectric layer and the upper electrode. A portion of a dielectric layer in the stacked capacitor portion is coupled to another dielectric layer formed on the surface of one impurity region. The capacitor has a planar type capacitor provided in the planar area of occupation of the stacked capacitor portion, whereby the capacitance of the capacitor can be increased without increasing the planar area of occupation.

Abstract: A field-effect transistor device comprising a p-type silicon substrate, a pair of n-channel MOS transistors, and a wiring means connecting the MOS transistors. The first MOS transistor has a gate electrode provided above the substrate and extending in one direction, and two regions formed in the substrate, located on two opposing sides of the gate electrode, and serving as a source and a drain. The second MIS transistor has a gate electrode provided above the substrate and extending in said one direction, and two regions formed in the substrate, located on two opposing sides of this gate electrode, and serving as a source and a drain. The wiring means includes bit lines BL and BL which permit the source-drain paths of the first and second MIS transistors to be oriented in the same direction.