Patents Examined by Courtney A. Bowers
  • Patent number: 5453627
    Abstract: A quantum interference device has semiconductor heterojunctions laminated on a semiconductor substrate for forming a two-dimensional electron gas channel. On the semiconductor heterojunctions are formed a first, a second and a third electrode which, upon the application of a negative voltage, form a depletion region within the semiconductor heterojunctions, thereby making the resulting two-dimensional electron gas channel a quantum wire of a stub structure comprising an entrance and an exit for electron waves, and a stub formed between the entrance and the exit. The second and third electrodes each have a first side substantially parallel to a side of the first electrode. The second and third electrodes also have a second side parallel to each other's second side. On a site near the edge of said stub is provided a fourth electrode for defining the effective length of the stub by a voltage applied thereto.
    Type: Grant
    Filed: May 12, 1993
    Date of Patent: September 26, 1995
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Kimihisa Aihara, Masafumi Yamamoto, Takashi Mizutani
  • Patent number: 5449936
    Abstract: A high current MOS transistor integrated bridge structure includes at least two arms, each having a first and a second MOS transistor. The structure is formed on an N++ substrate forming a positive potential output terminal, and an N-type epitaxial layer. For each first transistor, an L shaped region is formed of a horizontal N+ region which is connected to the surface through an N++ vertical region. Forming a corresponding alternating current input with this region is an N type region which has within it a succession of P type regions, and a pair of N+ type regions forming a negative potential output terminal. For each second transistor, an N+ region has N++ lateral regions extending to the surface, and includes an N type region containing a succession of P type regions and a pair of N+ regions forming corresponding alternating current inputs. The first transistor of each arm is entirely contained within a P type isolation region which has P+ regions extending to the surface of the substrate.
    Type: Grant
    Filed: September 21, 1994
    Date of Patent: September 12, 1995
    Assignees: SGS-Thompson Microelectronics Srl, Consorzio per la Ricerca Sulla Microelectronics nel Mezzogiorno
    Inventors: Mario Paparo, Natale Aiello
  • Patent number: 5449943
    Abstract: The light receiving or back-side surface (22) of an indium antimonide (InSb) photodetector device (10) substrate (12) is cleaned to remove all oxides of indium and antimony therefrom. Passivation and/or partially visible light blocking layers (26, 28) are then formed thereon of a material which does not react with InSb to form a structure which would have carrier traps therein and cause flashing. The optical cutoff wavelength and thickness of the partially visible light blocking layer (28) are selected to suppress the avalanche effect in the device (10) at visible wavelengths. This enables the device (10) to operate effectively over a wide wavelength range including the visible and infrared bands. The passivation and/or partially visible light blocking layers (26, 28) may be a thin layer of a semiconductor such as germanium, or silicon dioxide and/or silicon nitride followed by a partially visible light blocking silicon layer.
    Type: Grant
    Filed: June 2, 1994
    Date of Patent: September 12, 1995
    Assignee: Santa Barbara Research Center
    Inventors: Ichiro Kasai, Herbert L. Hettich, Stephen L. Lawrence
  • Patent number: 5449927
    Abstract: A layer (32) of a HgCdTe compound epitaxially contacts a buffer structure, which in turn epitaxially contacts a silicon substrate (22). The buffer structure is formed of II-VI compounds, and preferably includes at least one layer (24) of a ZnSeTe compound epitaxially contacting the silicon substrate (22) and a layer (30) of a CdZnTe compound overlying the ZnSeTe compound layer (24). The ZnSeTe compound layer (24) may be provided as a single graded layer having a composition of ZnSe adjacent to the silicon and a composition of ZnTe remote from the silicon, or as two distinct sublayers with a ZnSe sublayer (26) adjacent to the silicon substrate (22) and a ZnTe sublayer (28) remote from the silicon substrate (22).
    Type: Grant
    Filed: May 16, 1994
    Date of Patent: September 12, 1995
    Assignee: Santa Barbara Research Center
    Inventors: William J. Hamilton, Jr., Scott M. Johnson, William L. Ahlgren
  • Patent number: 5449929
    Abstract: A method of producing on a substrate an in-plane-gate transistor includes producing a channel portion in which a quasi-one-dimensional conductive channel electrically connecting a source region and a drain region is generated and producing gate portions, each portion including a gate electrode layer for controlling generation and forfeiture of the quasi-one-dimensional conductive channel so that an upper surface of the gate layer and the quasi-one-dimensional conductive channel are positioned substantially in the same plane, on both sides of the channel portion on the substrate. Gaps between the channel portion and the gate portions are controlled by side walls produced self-aligningly on the side wall surfaces of the channel portion. Thus, gaps of a high aspect ratio can be produced between the channel portion and the gate portions without being limited by the dry etching technique.
    Type: Grant
    Filed: December 20, 1993
    Date of Patent: September 12, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kenji Hosogi
  • Patent number: 5448386
    Abstract: An electro-optic element, such as a liquid crystal, exhibits optical rotatory dispersion and includes a pair of phase difference films which have generally orthogonal stretching axes and are disposed between a pair of polarizing plates. The stretching axis directions of the phase difference films and the transmission axis directions of the polarizing plates are arranged relative to the molecular orientation of the surfaces of the liquid crystal cell to achieve an increase in the angle of visibility, an increase in contrast and improvements in color tones.
    Type: Grant
    Filed: July 12, 1993
    Date of Patent: September 5, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroshi Watanabe, Nobuyasu Yamagishi, Kazuo Yokoyama
  • Patent number: 5448084
    Abstract: A field effect transistor including a substrate comprised of a material having a spinel crystal structure and a buffer layer lattice matched to the crystal structure of the substrate comprising gallium aluminum indium arsenide is described. Several types of field effect transistors are possible with the described substrate arrangement, including metal semiconductor field effect transistors, insulating gate field effect transistors, pseudomorphically strained and pseudomorphically strain compensated metal semiconductor field effect transistors, as well as, high electron mobility transistor structures.
    Type: Grant
    Filed: May 24, 1991
    Date of Patent: September 5, 1995
    Assignee: Raytheon Company
    Inventors: William E. Hoke, H. Jerrold Van Hook
  • Patent number: 5448098
    Abstract: A first type of superconductive photoelectric device is provided by a superconductive thin film located between two electrodes. The superconductive thin film is one which has a photo-conductive effect and converts from a normally conducting state to a superconductive state in response to light irradiation. The superconductive thin film is preferably formed of a compound semiconductor of Pb chalcogenide added with Pb and/or In added beyond the stoicheometry of the compound semiconductor, such as Pb.sub.1-x Sn.sub.x Te+In, so as to generate precipitations of Pb. A second type of superconductive photoelectric device is provided by a photo-conductive material formed of Pb.sub.1-x Sb.sub.x Te filled in a gap between two superconductive electrodes, where the gap width is shorter than 500 times of a coherence length.
    Type: Grant
    Filed: August 25, 1992
    Date of Patent: September 5, 1995
    Assignee: Fujitsu Limited
    Inventors: Koji Shinohara, Osamu Ohtsuki, Kazuo Murase, Sadao Takaoka
  • Patent number: 5442225
    Abstract: Apparatus for improving ON/OFF switching in high speed digital circuitry is disclosed. The present invention includes apparatus for altering the impedance or capacitive loading of the interconnect. Some embodiments reduce back reflections by raising the impedance of the interconnect to be closer to that of the contact, or raising the capacitive loading, and others improve the culprit-victim problem by filtering out the highest frequency components of the pulse on the culprit interconnect. For the back reflection problem, the apparatus for altering can be formed of elements for altering the capacitance or, alternatively the resistance, of the interconnect. For the culprit-victim problem, the apparatus for altering includes elements which alter the effective capacitance or resistance of the culprit interconnect.
    Type: Grant
    Filed: August 13, 1993
    Date of Patent: August 15, 1995
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch
  • Patent number: 5440160
    Abstract: A high saturation current, low leakage, Fermi threshold field effect transistor includes a predetermined minimum doping concentration of the source and drain facing the channel to maximize the saturation current of the transistor. Source and drain doping gradient regions between the source/drain and the channel, respectively, of thickness greater than 300 .ANG. are also provided. The threshold voltage of the Fermi-FET may also be lowered from twice the Fermi potential of the substrate, while still maintaining zero static electric field in the channel perpendicular to the substrate, by increasing the doping concentration of the channel from that which produces a threshold voltage of twice the Fermi potential. By maintaining a predetermined channel depth, preferably about 600 .ANG., the saturation current and threshold voltage may be independently varied by increasing the source/drain doping concentration facing the channel and by increasing the excess carrier concentration in the channel, respectively.
    Type: Grant
    Filed: January 5, 1994
    Date of Patent: August 8, 1995
    Assignee: Thunderbird Technologies, Inc.
    Inventor: Albert W. Vinal
  • Patent number: 5432373
    Abstract: A magnetic spin transistor, usable as a memory cell, magnetic pick-up head, or a current switch, that includes a trilayer planar structure of a conductive, nonferromagnetic layer (16) sandwiched between two ferromagnetic layers (12, 14) of different coercivities. A biasing current pumped between one of the ferromagnetic layers and the nonferromagnetic layers produces a voltage on the other ferromagnetic layer. The polarity of the voltage depends on the relative magnetic polarization of the two ferromagnetic layers. As a memory cell, current passing through adjacent lines magnetize the ferromagnetic layer of lower coercivity. As a magnetic pick-up head, an adjacent magnetic recording track supplies the magnetic field sufficient to switch the lower-coercivity ferromagnetic layer.
    Type: Grant
    Filed: November 29, 1994
    Date of Patent: July 11, 1995
    Assignee: Bell Communications Research, Inc.
    Inventor: Mark B. Johnson
  • Patent number: 5428229
    Abstract: A MOS semiconductor device which exhibits high switching operations including high turn-on and an excellent self-cooling capability. The device prevents damage to insulation films and electrodes thereof. An IGT includes a multi-layer structure having a p type emitter layer, an n type base layer, a p type base layer and an n type emitter layer superimposed therein. A gate electrode and an overlying gate oxide film are disposed on a recessed surface of the multi-layer structure. A cathode electrode is located only in and around a cathode surface so that most of the top surface of the gate electrode is uncovered. Via an intervening cathode distortion snubbering plate, the cathode electrode is in pressure contact with a cathode electrode body. The gate and the cathode electrodes have a reduced capacitance therebetween. The cathode electrode body serves to cool the cathode electrode. The gate electrode and the gate oxide film are protected from stress, and hence, will not be damaged by stress.
    Type: Grant
    Filed: October 18, 1994
    Date of Patent: June 27, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuhiko Niwayama, Futoshi Tokunou
  • Patent number: 5428249
    Abstract: A photovoltaic device of this invention has a semiconductor layer for generating a photovoltaic power and a collector electrode formed on the semiconductor layer to collect the power generated by the semiconductor layer. A conductive layer containing a conductive powder is formed on at least one side of the collector electrode closer to the semiconductor layer, and a metal layer is formed on the side away from the semiconductor layer. The metal layer covers the surface of the conductive layer away from the semiconductor layer.
    Type: Grant
    Filed: July 12, 1993
    Date of Patent: June 27, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ippei Sawayama, Hitoshi Toma, Yoshihiko Hyosu, Tatsuo Fujisaki, Toshihiko Mimura
  • Patent number: 5428235
    Abstract: A memory cell of a DRAM comprises one MOS transistor and one capacitor. The MOS transistor includes a pair of source/drain regions and a gate electrode formed on the channel region. A bit line is formed so as to be connected to the source/drain region. A conductive layer is formed so as to be connected to the source/drain region. The gate electrode includes a first part formed on the channel region with an oxide film interposedand second and third parts extending from the first part, respectively, and formed on the bit line and the conductive layer with an interlayer oxide film interposed. The capacitor includes a lower electrode formed so as to be connected to the conductive layer and an upper electrode formed so as to be opposed to the surface of the lower electrode with a dielectric film interposed. The upper electrode is placed above the bit line. A word line is placed above the upper electrode and connected to the gate electrode.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: June 27, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masahiro Shimizu, Takehisa Yamaguchi, Natsuo Ajika
  • Patent number: 5428250
    Abstract: The line material is of a laminated structure consisting of: a Ta containing N alloy layer (lower layer) which is a first metal layer made of at least an alloy selected from the group consisting of a TaN alloy, a Ta--Mo--N alloy, a Ta--Nb--N alloy and a Ta--W--N alloy; a second metal layer (upper layer) formed integrally with the first metal layer and made of at least an alloy selected from the group consisting of Ta, a Ta--Mo alloy, a Ta--Nb alloy, a Ta--W alloy, a TaN alloy, a Ta--Mo--N alloy, a Ta--Nb--N alloy and a Ta--W--N alloy; and/or a pin hole-free oxide film. The line material of the laminated structure is to be applied to the formation of signal lines and electrodes of, e.g., a liquid crystal display. The line material has a low resistance and the insulating film formed by anodization and the like exhibits excellent insulation and thermal stability. Therefore, when the line material is applied to signal lines of various devices, it exhibits excellent characteristics.
    Type: Grant
    Filed: July 22, 1993
    Date of Patent: June 27, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsushi Ikeda, Michio Murooka
  • Patent number: 5424567
    Abstract: A programmable transistor includes impurity regions to reduce punch-through and soft-write phenomena. In order to provide a fast operation, the impurity regions are arranged with regard to one another so that parasitic capacitances at junctions of impurity regions of mutually opposite conductivity type are minimized. For these purposes, the transistor comprises a charge storage region over a channel region in a main semiconductor zone of a first conductivity type located between a source and a drain of a second conductivity type opposite to the first. A first impurity zone of the first conductivity type, substantially laterally contiguous with the drain, extends into the channel region and is more heavily doped than the main zone. The drain includes a heavily doped third impurity region and a lightly doped second impurity region that lies at least mainly between the third region and the zones.
    Type: Grant
    Filed: May 15, 1991
    Date of Patent: June 13, 1995
    Assignee: North American Philips Corporation
    Inventor: Teh-Yi J. Chen
  • Patent number: 5420459
    Abstract: A resin encapsulation type semiconductor device is provided with first leads electrically connected to the signal terminals of a semiconductor element and plate-like conductor elements electrically connected to the power source terminals of the semiconductor element. The first leads and the plate-like conductor elements are arranged in parallel with each other to form a two-layer structure. The number of the leads of the semiconductor element of the invented semiconductor device is reduced from that of the leads of the conventional semiconductor device. At least one through hole is formed in each of the plate-like conductor elements in a power source lead frame so as to make the flow distribution more uniform than in the plate-like conductor elements without the through holes.
    Type: Grant
    Filed: October 22, 1993
    Date of Patent: May 30, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Kozono
  • Patent number: 5416356
    Abstract: An integrated circuit is formed from a first layer of conductive material (30) which is separated from a second layer of conductive material (39) by a layer of dielectric material (36). The first layer of conductive material (30) is patterned to form a first plate (32, 59) of a capacitor (22, 50, 62, 72). An electrical interconnect (33, 63) is formed within the first plate (32, 59), respectively. A via (37) is formed in the layer of dielectric material (36). A second layer of conductive material (39) is patterned to form a second plate (42, 56, 66, 76) of the capacitor (22, 50, 62, 72) and a planar spiral inductor (21, 51, 61, 71). The planar spiral inductor (21, 51, 61, 71) is surrounded by the second plate (42, 56, 66, 76) of the capacitor (22, 50, 62, 72).
    Type: Grant
    Filed: September 3, 1993
    Date of Patent: May 16, 1995
    Assignee: Motorola, Inc.
    Inventors: Joseph Staudinger, Warren L. Seely, Howard W. Patterson
  • Patent number: 5410185
    Abstract: A bridging contact between internal contacts in a semiconductor integrated circuit is formed which is insulated from any connection to an intervening feature. A first dielectric layer is deposited over the contacts and the intervening feature, followed by an etch stop layer. The etch stop layer is patterned to form an etch stop mask and a second dielectric layer is deposited over the first dielectric layer and the patterned etch stop. The first and second dielectric layers are etched to form a trench opening and a pair of communicating passageways in the dielectric layers which expose the internal contacts. The etch stop mask protects and controls the vertical and horizontal dimensions of the resultant dielectric insulator that protects the intervening feature. Metal is deposited in the opening and passageways to form a bridging contact between the contacts. The bridging contact is electrically isolated from the intervening feature by the dielectric insulator remaining over and around the intervening feature.
    Type: Grant
    Filed: December 20, 1993
    Date of Patent: April 25, 1995
    Inventor: Jenn L. Yeh
  • Patent number: 5410167
    Abstract: A silicon nitride film 2 is formed on a GaAs substrate 1 and patterned to selectively expose the GaAS substrate surface in uniformly distributed areas having a width of not greater than 1 .mu.m. A non-doped GaAs buffer layer is grown on the GaAs substrate to completely cover the silicon nitride film. Then, a semiconductor multilayer structure including a non-doped GaAs layer is formed on the non-doped GaAs buffer layer. When a semiconductor integrated circuit device is manufactured using this semiconductor substrate, side gate effect can be effectively reduced due to the existence of the silicon nitride pattern and the buffer layer.
    Type: Grant
    Filed: July 9, 1993
    Date of Patent: April 25, 1995
    Assignee: Fujitsu Limited
    Inventor: Junji Saito