Abstract: An adjustable CCD gate structure utilizing ultra-violet light activated floating gates, wherein a floating polysilicon gate is used between a CCD electrode and the underlying substrate to provide a fixed voltage bias to the CCD gate during the manufacturing process thereof The floating gate is programmed with a desired voltage bias during the application of ultra-violet light and is thereafter fixed at that adjusted level, upon the removal of the ultra-violet light.

Abstract: A semiconductor device of improved ruggedness is provided which comprises a semiconductor substrate having a region of a first conductivity type on a major surface thereof; a first base region of opposite conductivity type formed selectively within said regions of first conductivity type; a second base region of opposite conductivity type formed selectively within said first base region and having a higher impurity concentration than that of said first base region; a source region of one conductivity type formed within said first and second base regions and overlying said second base region; and a polysilicon gate electrode opposed to a channel region with a gate insulating layer interposed therebetween; wherein the second base region and the source region are formed substantially entirely within the first base region; the second base region is smaller in depth than the first base region and is formed at a distance sufficiently close to the channel region to effectively reduce parasitic resistance in the firs

Abstract: A compound semiconductor device wherein a contact to an n type Al.sub.x Ga.sub.1-x As layer comprises an In.sub.x Ga.sub.1-x As graded-composition layer, an In.sub.x Ga.sub.1-x As contact layer having a constant composition and a metal electrode layer, the In.sub.x Ga.sub.1-x As graded-composition layer is doped with an n type impurity which concentration is higher than a concentration of an impurity activated as n type, whereby, even when a thickness of the In.sub.x Ga.sub.1-x As graded-composition layer is made sufficiently small, a reduction in the carrier concentration of the thin graded-composition layer causes no increase of its resistance and a low-resistance contact is realized.

Abstract: A thin-film electroluminescence device has transparent electrodes formed on a transparent substrate, a lower dielectric layer formed on the substrate having the transparent electrodes, a luminescent layer formed on the lower dielectric layer, an upper dielectric layer formed on the luminescent layer, and back electrodes formed on the upper dielectric layer. At least one of the upper and lower dielectric layers includes a SiN:H film formed in contact with the luminescent layer by a plasma chemical vapor deposition method. The SiN:H film contains N--H bonds of 1.2.times.10.sup.22 /cm.sup.3 or less to control an amount of change in emission-start voltage to 30 V or less.

Abstract: The line material is of a laminated structure consisting of: a Ta containing N alloy layer (lower layer) which is a first metal layer made of at least an alloy selected from the group consisting of a TaN alloy, a Ta-Mo-N alloy, a Ta-Nb-N alloy and a Ta-W-N alloy; a second metal layer (upper layer) formed integrally with the first metal layer and made of at least an alloy selected from the group consisting of Ta, a Ta-Mo alloy, a Ta-Nb alloy, a Ta-W alloy, a TaN alloy, a Ta-Mo-N alloy, a Ta-Nb-N alloy and a Ta-W-N alloy; and/or a pin hole-free oxide film. The line material of the laminated structure is to be applied to the formation of signal lines and electrodes of, e.g., a liquid crystal display. The line material has a low resistance and the insulating film formed by anodization and the like exhibits excellent insulation and thermal stability. Therefore, when the line material is applied to signal lines of various devices, it exhibits excellent characteristics.

Abstract: The present invention, which is directed to a light-emitting diode array for use as the light source in optical printers and other such applications, provides improved optical efficiency and a more uniform distribution of emission intensity. The light-emitting diodes are formed as reverse mesas with a mirrored sloping surface that reflects light in the direction of the light emitting surface of the diode. This improves the emission efficiency of each diode. In addition, this also increases the light output from the edge portions of light-emitting surfaces of the diodes so as to produce a more uniform distribution of light output from the light-emitting diodes.

Abstract: On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.- epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer.

Abstract: A circuit test of a semiconductor device having a redundant circuit for repairing defective circuit is carried with the fuse portion (21) of the redundant circuit and the bonding pad portion (26) exposed and the wiring layers (23) formed on the semiconductor substrate protected with a first protective layer (32). By this step, metal shavings (29) scraped from the surface of the bonding pad by a tester electrode terminal during the circuit test can be prevented from being directly in contact with the interconnection layers, whereby generation of short circuit can be prevented. Thereafter, the surfaces of the bonding pad portion and the fuse portion are covered with a second protective layer (33) and a third protective layer (25) (polyimide). The surface of the bonding pad portion is exposed by etching.

Abstract: A transistor is formed as either a bipolar transistor (10) or an MOS transistor (11). Each transistor (10 or 11) has a substrate (12). Bipolar transistor (10) has a first current electrode (26) underlying a control electrode (28), and a second current electrode (32) overlying the control electrode (28). MOS transistor (11) has a first current electrode (54) underlying a channel region (56), and a source lightly doped region (58) and a source heavily doped region (60) overlying the channel region (56). A control electrode conductive layer (40) is laterally adjacent a sidewall dielectric layer (48), and sidewall dielectric layer (48) is laterally adjacent channel region (56). Conductive layer (40) functions as a gate electrode for transistor (11). Each of the transistors (10 and 11) is vertically integrated such as in a vertically integrated BiMOS circuit. Transistors (10 and 11) can be electrically isolated by isolation ( 64 and 66).

Abstract: A high density nonvolatilized semiconductor integrated circuit is comprised of a Dynamic RAM (DRAM) cell unit and a nonvolatile cell unit. The DRAM cell unit is comprised of a first transistor having its gate connected to a word line, its source connected to a bit line and its drain connected to a first capacitor. The first capacitor has its other electrode connected to a first line. The nonvolatile RAM cell unit is comprised of a second transistor having its gate connected to a second line, its source connected to the bit line and its drain connected to a second capacitor. The second capacitor has its other electrode connected to a third line. The second capacitor comprises a ferroelectric substance to which a reverse voltage is applied in order to read out its signal, and the first capacitor comprises a paraelectric substance to which such reverse voltage is not applied. The cycle life of the DRAM cell unit is thereby increased.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a field insulation film formed on a surface of the semiconductor substrate by a selective thermal oxidation process employing an oxidation-resistant mask whereby first and second groups of openings are formed therein for exposing the substrate at predetermined locations respectively corresponding to first and second active regions and relative to which first and second groups of contact holes are to be formed.

Abstract: A photoelectric converting device has non-monocrystalline semiconductor layers of PIN structure laminated on mutually isolated plural pixel electrodes. P- or N-doped layer on the pixel electrode contains at least a microcrystalline structure. N- or P-doped layer on the area other than the pixel electrode is amorphous.

Abstract: A dynamic random access memory comprises a memory cell region and a sense amplifier region defined on a substrate, a plurality of memory cell capacitors provided on the memory cell region in correspondence to memory cell transistors, a first insulation layer provided on the semiconductor substrate to cover both the memory cell region and the sense amplifier region, a first conductor pattern provided on the first insulation layer, an intermediate connection pattern provided on the first insulation layer in correspondence to the sense amplifier region, a spin-on-glass layer provided on the first insulation layer to extend over both the memory cell region and the sense amplifier region, and a projection part provided on the substrate of the sense amplifier region in correspondence to the intermediate connection pattern under the first insulation layer for lifting the level of the surface of the first insulation layer such that the intermediate interconnection pattern is exposed above the upper major surface of t

Abstract: A pair of first and second thin film transistors (TFTs). The transistors are formed from a first continuous, conductive region (38) and a second continuous, conductive region (39) which underlies the first conductive region (38). The first transistor has a source region (50), a drain region (54), and a channel region (52) created from three distinct and separate regions of conductor region (39). The first transistor has a gate region (53) that overlies the channel region (52). The gate region (53) is formed from a distinct region of conductive region (38). The second transistor has a source region (44), a drain region (48), and a channel region (46) which are created from three distinct and separate regions of conductor region (38). The second transistor has a gate region (47) that underlies the channel region (46). The gate region (47) is formed from a distinct region of conductive region (39).

Abstract: A thin-film transistor comprises a gate electrode formed on a glass substrate, a gate insulating film formed essentially over an entire surface of the substrate to cover the gate electrode, a non-single-crystal silicon semiconductor film placed on the gate insulating film to cover the gate electrode; and a drain electrode and a source electrode spaced a specified distance apart on the semiconductor film and electrically connected to the semiconductor film so as to form the channel region of the transistor. The gate electrode is made of titanium-containing aluminum.

Abstract: A buried Zener diode has an auxiliary Zener junction access path in parallel with the force anode/cathode path. Unlike the force anode/cathode path, the auxiliary path is effectively by-passed by the current flowing between the force anode and cathode during circuit operation, so that there is no accumulation of significant resistance-current products that would otherwise mask the Zener voltage. The Zener diode has an anode region disposed in a first surface portion of a substrate. A `force` anode is formed on a first surface portion of the anode region. A `sense` anode is disposed on a second surface portion of the anode region spaced apart from the force anode. A first cathode region is disposed in a second surface portion of the substrate spaced apart from the anode region, while a sense cathode region is disposed in a third surface portion of the substrate spaced apart from each of the anode region and the first cathode region.

Abstract: A power semiconductor device is constructed by integrating a DMOS transistor and a lateral MOS transistor on the same semiconductor chip. The lateral MOS transistor is formed within a well with a conductivity type which is the same as the conductivity type of the source region of the DMOS transistor. The gate voltage is monitored at the time of connecting the gate and the drain of the lateral MOS transistor and of driving it at a constant current. When the gate voltage drops below a predetermined value, the driving of the DMOS transistor is stopped. The breakdown of the power semiconductor device due to heating can thus be prevented.

Abstract: An image projection arrangement is disclosed, comprising a radiation source (1), an image display system having at least one image display panel (10) in which the polarisation direction of an incident beam is modulated with the image information, and a polarisation-sensitive beam splitter (2), arranged between the source and the image display system, for forming two mutually perpendicularly polarised sub-beams (b.sub.1, b.sub.2). By having the two sub-beams be modulated by the same image display system (10) and by thereafter combining these sub-beams again a very efficient use can be made of the available light without the necessity of a significant more complex design of the arrangement.

Abstract: A liquid crystal apparatus, includes: a) a liquid crystal device comprising an electrode matrix composed of scanning electrodes and data electrodes, and a ferroelectric liquid crystal showing a first and a second orientation state; and b) a driving means including: a first drive means for applying a scanning selection signal to the scanning electrodes two or more scanning electrodes apart in one vertical scanning so as to effect one picture scanning in plural times of vertical scanning, said scanning selection signal having a voltage of one polarity and a voltage of the other polarity with respect to the voltage level of a nonselected scanning electrode, and a second drive means for applying to a selected data electrode a voltage signal which provides a voltage causing the first orientation state of the ferroelectric liquid crystal in combination with the voltage of one polarity of the scanning selection signal, and applying to another data electrode a voltage signal which provides a voltage causing the secon

Abstract: A semiconductor device includes a plurality of gate electrodes (6a, 6b, 6c, 6d) arranged on the surface of a semiconductor substrate (1) with insulating layers (5, 8) covering the top and the side walls of the gate electrodes. The spaces between the opposing side walls of adjacent gate electrodes on the surface of the element isolation region (2) re smaller than twice the thickness of the thinnest insulating layer (8) among the insulating layers of the side walls of the gate electrodes on the surface of the active regions. The space (14) between the gate electrodes on the element isolation region is filled with the insulating isolation layer (8) so that unevenness in the underlying portion on the element isolation region on which the conductive interconnection layer (10) to be formed is reduced, preventing thinning of the conductive interconnection layer and disconnection due to excessive etching of a resin film in patterning the conductive interconnection layer.