Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

Abstract: Provided are a storage device, a storage system, and a method of operating the same. A storage device communicably connected to a host may include a non-volatile memory configured to store at least one piece of boot data necessary for booting the storage device; and a device controller configured to receive an interface initialize command (IFIC) from the host, predict requested boot data requested by the host from among the at least one piece of boot data based on the IFIC, and control the non-volatile memory to read the requested boot data.

Abstract: A data storage method is provided according to an exemplary embodiment of the disclosure. The method is configured for a rewritable non-volatile memory module. The method includes: performing a data merge operation; adjusting a data receiving amount per unit time for receiving to-be-written data from a host system according to a data storage state of the rewritable non-volatile memory module; storing the received to-be-written data into a buffer memory during the data merge operation being performed; and storing the data stored in the buffer memory into the rewritable non-volatile memory module.

Abstract: Techniques for data processing a data set may comprise: performing first processing that forms a first compression unit, wherein the first compression unit includes a data chunks including a first data chunk having a first entropy value less than an entropy threshold, the first processing including: receiving a second data chunk; determining, in accordance with criteria, whether to add the second data chunk to the first compression unit; and responsive to determining to add the second data chunk to the first compression unit, adding the second data chunk to the first compression unit; and compressing the first compression unit as a single compressible unit. The second chunk may be added if its entropy value is less than the entropy threshold and if entropy values of the first and second chunks are similar. The second chunk may be added if the resulting compression unit provides sufficient storage/compression benefit.

Abstract: A virtual storage system according to an aspect of the present invention includes multiple storage systems each including: a storage controller that accepts a read/write request for reading or writing from and to a logical volume; and multiple storage devices. The storage system defines a pool that manages the storage device capable of allocating any of storage areas to the logical volume, and manages the capacity (pool capacity) of the storage areas belonging to the pool, and the capacity (pool available capacity) of unused storage areas in the pool. Furthermore, the storage system calculates the total value of the pool available capacities of the storage systems included in the virtual storage system, and provides the server with the total value as the pool available capacity of the virtual storage system.

Abstract: Stage task control blocks (TCB) are allocated for performing staging operations in a storage controller controlling one or more storage ranks. Destage TCBs are allocated for performing destaging operations in the storage controller. The storage controller adjusts how many stage TCBs and destage TCBs are to be allocated based on response times of the one or more storage ranks.

Abstract: Devices and techniques for storage class memory status are disclosed herein. A storage portion characteristics data structure is maintained. Here, the data structure includes an array of elements—where each element is sized to contain a reference to a storage portion in a storage class memory storage device, a first pointer to a first element in the array of elements, a second pointer to a second element in the array of elements, and a third pointer to a third element in the array of elements. The data structure includes a direction of pointer motion in which the second pointer precedes the third pointer and the first pointer precedes the second pointer with respect to the direction of pointer motion. A write request is performed to a storage portion reference retrieved from the first element. The first pointer is then advanced.

Abstract: Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules that are evaluated using the state of the NAND device. In some examples, the SLC cache migration process may utilize a number of NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data.

Abstract: A method and apparatus is disclosed for using supervised learning with closed loop feedback to improvement of output consistency for memory arrangements, such as a solid state drive.

Abstract: Techniques perform data synchronization. The techniques involve: in response to writing of data to a source storage array, determining whether a transmission link between the source storage array and a destination storage array is disconnected, the data being to be synchronized to the destination storage array; in response to determining that the transmission link is disconnected, accumulating in the source storage array the data written to the source storage array; in response to detecting that the transmission link is recovered, creating a snapshot for a storage unit associated with the data in the destination storage array; and in response to crashing of the source storage array during resynchronization of the data accumulated in the source storage array to the storage unit, restoring the storage unit in the destination storage array using the snapshot. Therefore, the storage space for the snapshot is greatly saved while disaster recovery is ensured.

Abstract: A method for improving I/O response times in a data replication environment is disclosed. In one embodiment, such a method includes receiving, at a primary storage system, a request to read data on the primary storage system. The method starts a timer upon receiving the request. In the event the data cannot be retrieved from the primary storage system by the time the timer expires, the method requests the data from a secondary storage system. In the event the primary storage system returns the data before the secondary storage system, the method returns data retrieved from the primary storage system to a host system. In the event the secondary storage system returns the data before the primary storage system, the method returns the data retrieved from the secondary storage system to the host system. A corresponding system and computer program product are also disclosed.

Abstract: Methods that can dynamically merge parity data for multiple data stripes are provided. One method includes detecting, by a processor, a disk failure in a redundant array of independent disks (RAID) configuration and, in response to detecting the disk failure, merging parity data stored in a plurality of sets of segments in a stripe of the RAID configuration to free space in a set of parity segments of the plurality of sets of segments. Systems and computer program products for performing the method are also provided.

Abstract: A system and method for offset protection data in a RAID array. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to store user data in a first page of a first storage device of the plurality of storage devices; generate intra-device protection data corresponding to the user data, and store the intra-device protection data at a first offset within the first page. The controller is further configured to generate inter-device protection data corresponding to the first page, and store the inter-device protection data at a second offset within a second page in a second storage device of the plurality of storage devices, wherein the first offset is different from the second offset.

Abstract: A system and method for offset protection data in a RAID array. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to store user data in a first page of a first storage device of the plurality of storage devices; generate intra-device protection data corresponding to the user data, and store the intra-device protection data at a first offset within the first page. The controller is further configured to generate inter-device protection data corresponding to the first page, and store the inter-device protection data at a second offset within a second page in a second storage device of the plurality of storage devices, wherein the first offset is different from the second offset.

Abstract: Embodiments of the present invention provide tightly coupled off-die memory along with an interface bus and smart buffer logic so as to efficiently perform certain frequent or repetitive operations off of a core logic. Embodiments of the present invention relieve the core logic from performing certain repetitive or frequent memory accesses and other operations so as to allow such core logic to perform other more general or varied operations. In this way, the universal interface bus, smart buffer logic, and off-die memory are specially configured to perform certain select frequent and repetitive operations while the core logic may configured to perform other operations so as to provide an improved configuration with increased computational capability and reduced power budget.

Abstract: A method for a virtual machine executed by a hypervisor includes identifying, for the virtual machine, mappings between a range of guest virtual addresses (GVAs) and a range of guest physical addresses (GPAs) that remain the same in an initial guest page table for a threshold period of time, creating an intermediate guest page table including one or more page table entries that map the range of the GVAs to a range of guest intermediate addresses (GIAs), and causing the GVA to be translated to a GIA using the intermediate guest page table in view of the one or more page table entries, where the translation is triggered responsive to a guest application of the virtual machine attempting to access a GVA in the range of the GVAs.

Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

Abstract: A method for recovering data for a file system includes a journal-less recovery process that detects one or more inconsistencies for file system blocks upon a system failure based on one or more comparisons of information for the file system blocks.

Abstract: The present application provides a method of randomly accessing a compressed structure in memory without the need for retrieving and decompressing the entire compressed structure.