Patents Examined by Craig S Goldschmidt
  • Patent number: 12293090
    Abstract: A storage device is disclosed. The storage device may include a storage for a data and a controller to manage access to the data in the storage. A mechanism may automatically manage a bias mode for a chunk of the data in the storage, the bias mode including one of a host bias mode and a device bias mode.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: May 6, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Vincent Tung Pham, Andrew Zhenwen Chang
  • Patent number: 12293107
    Abstract: A memory accessed by rows and/or by columns in which an array of bits can be physically stored physical one-bit wide columns with each bit of the multi-bit wide logical column stored in a one-bit physical column in a different physical die. The multi-bit column is read by reading a one-bit physical column in each of the different physical die in parallel. The multi-bit wide logical column is arranged diagonally across M physical rows and M one-bit physical columns with each bit of the multi-bit wide logical column in the logical row stored in a different physical row and physical one-bit wide column in one of plurality of dies.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: May 6, 2025
    Assignee: Intel Corporation
    Inventors: Chetan Chauhan, Sourabh Dongaonkar, Jawad B. Khan
  • Patent number: 12282670
    Abstract: Provided is a storage system and a storage management method, aiming at reducing data movement amount necessary for using an expanded capacity in a distributed RAID. When only A (A is a positive integer) physical storage drives are added, a storage controller selects virtual parcels that are mapped to different physical storage drives among N physical storage drives and are included in different virtual chunks, changes an arrangement of the selected virtual parcels to the added A physical storage drives, and constitutes a new chunk based on unallocated virtual parcels selected from different physical storage drives among the (N+A) physical storage drives.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: April 22, 2025
    Assignee: HITACHI VANTARA, LTD.
    Inventors: Hiroki Fujii, Yoshinori Ohira, Takeru Chiba, Yoshiaki Deguchi
  • Patent number: 12265467
    Abstract: Enhanced methods for memory context restore are described. A device may include a physical layer (PHY) having an interface to support communication of command signals and data with a physical memory. The PHY implements a training mode to train the interface, detect values of a plurality of parameters as part of training the interface, and store the detected values as initial training data. The PHY also implements a retraining mode to use the initial training data as seed data to retrain the interface.
    Type: Grant
    Filed: September 29, 2023
    Date of Patent: April 1, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anwar Parvez Kashem, Alicia Wen Ju Yurie Leong, Glennis Eliagh Covington
  • Patent number: 12265739
    Abstract: The present invention discloses a data access interface unit comprising: a physical storage device controller for receiving a first control signal from a first storage virtualization controller, and accordingly determining the first storage virtualization controller as the primary controller, and generating a first selection signal; a selector for receiving the first selection signal, and accordingly selecting data and signals from the first storage virtualization controller; and a clock generation circuit for providing a dedicated clock signal to the physical storage device, where when the physical storage device controller receives a re-set signal from a second storage virtualization controller, the physical storage device controller determines the second storage virtualization controller as the new primary controller, and accordingly generates a second selection signal so as to control the selector to select data and signals from the second storage virtualization controller.
    Type: Grant
    Filed: November 22, 2023
    Date of Patent: April 1, 2025
    Assignee: Infortrend Technology, Inc.
    Inventors: Yen-Chen Wu, Ying-Wen Lin, Chih-Min Hsiao
  • Patent number: 12260117
    Abstract: Apparatus and method for executing controller memory buffer (CMB) based data transfer commands in a distributed data processing environment. In some embodiments, a storage device having a device controller and a main non-volatile memory (NVM) is coupled to a client device via an interface. The client device respectively issues normal data transfer commands and bypass data transfer commands to the storage device. The normal data transfer commands include read and write commands that result in transfer of data between the NVM and the client device using a normal data path through the storage device. The bypass data transfer commands involve an allocated CMB of the storage device directly controlled and accessed by the client device. In this way, write data are directly placed into the CMB for writing to the NVM, and readback data from the NVM are directly recovered from the CMB by the client device.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: March 25, 2025
    Assignee: Seagate Technology, LLC
    Inventors: Phillip R. Colline, Timothy Ted Walker, Steven Williams, Hemant Vitthalrao Mane, Jason Matthew Feist
  • Patent number: 12254214
    Abstract: An input output control device between a verification circuit and a semiconductor memory device includes: a first port that receives a read transaction for requesting reading of data in the semiconductor memory device from the verification circuit, and outputs a read response to the verification circuit; a second port that outputs the read transaction to the semiconductor memory device, and receives the read response output from the semiconductor memory device in response to the read transaction; and a buffer device that delays at least one of an output of the read transaction to the semiconductor memory device and an output of the read response to the verification circuit.
    Type: Grant
    Filed: September 27, 2023
    Date of Patent: March 18, 2025
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, MIRISE Technologies Corporation
    Inventor: Tetsuro Takizawa
  • Patent number: 12254221
    Abstract: According to a magnetic disk apparatus of one embodiment, threshold voltages of memory cell transistors of a flash memory are set to a first section for a first value or to a second section for a second value. The second section is on a lower voltage side than the first section. The controller performs bit inversion of second data held in a volatile memory and writes the second data onto the flash memory when a power loss occurs while the second data corresponds to third data in which a number of the first values is larger than that of the second values. The controller writes the second data onto the flash memory without bit inversion when a power loss occurs while the second data corresponds to fourth data. The fourth data is data in which a number of the first values is smaller than that of the second values.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: March 18, 2025
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Keigo Sogabe
  • Patent number: 12254184
    Abstract: A method comprising: receiving a first workload data set, the first workload data set specifying a cache hit outcome distribution that is associated with a plurality of input-output (I/O) operations; identifying a plurality of workload portions of the first workload data set, each of the workload portions identifying: (i) a rate of a cache hit outcome that is associated with a respective I/O operation, and (ii) a data size that is associated with the respective I/O operations; generating a plurality of initial vectors, each of the initial vectors being generated based on a different one of the plurality of workload portions, each of the initial vectors being generated by a different sub-network of a correlation neural network; generating a context vector based on the plurality of initial vectors; processing the context vector with a decoder to generate a plurality of data points in a response curve of a storage system.
    Type: Grant
    Filed: January 24, 2024
    Date of Patent: March 18, 2025
    Assignee: Dell Products L.P.
    Inventors: Krzysztof Misan, Ron Arnan, Hagay Dagan, Gil Ratsaby
  • Patent number: 12248395
    Abstract: A data storage device and method are provided for predictable low-latency in a time-sensitive environment. In one embodiment, a data storage device is provided comprising a memory and a controller configured to communicate with the memory. The controller is further configured to: receive, from a host, an indication of a logical block address range that the host will later read; and in response to receiving the indication: read data from the logical block address range; and perform an action on the data to reduce a read latency when the host later reads the logical block address range. Other embodiments are disclosed.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: March 11, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Devika Nair, Amit Sharma
  • Patent number: 12248677
    Abstract: A data processing system includes data processing devices each including a computing memory and configured to perform a task; one or more host devices connected to the data processing devices, and each configured to: select one or more of the data processing devices based on meta information including a size of a memory, and sizes of the computing memories of the respective data processing devices, and request the selected processing devices to perform a first task; a network switch configured to connect the one or more host devices to the data processing devices; and a network manager in the network switch and configured to: collect free memories of the respective data processing devices based on the meta information and the sizes of the computing memories of the respective data processing devices, and control the one or more host devices to use some of the free memories.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 11, 2025
    Assignee: SK hynix Inc.
    Inventors: Jung Min Choi, Sun Woong Kim
  • Patent number: 12236122
    Abstract: A virtual storage volume may be implemented as one or more chunks stored on a set of storage nodes. The virtual storage volume may be dynamically adjusted by adjusting the one or more chunks that make up the virtual storage volume, without taking the virtual storage volume offline. Such dynamic volume adjustment may allow for increasing volume size without moving data unnecessarily. In addition or alternatively, such dynamic volume adjustment may free up storage space in a node with minimum movement of data.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: February 25, 2025
    Assignee: Pure Storage, Inc.
    Inventors: Ganesh Sangle, Vinod Jayaraman
  • Patent number: 12229433
    Abstract: Techniques are provided for storage system interface discovery with a limited number of persistent host discovery connections. One method comprises receiving, by a receiving storage system interface of multiple storage system interfaces, a discovery connection request from a given host interface; transforming, by the receiving storage system interface, an identifier of a host device associated with the given host interface to obtain an identifier of a given storage system interface; determining, by the receiving storage system interface, whether the identifier of the given storage system interface identifies the receiving storage system interface; and in response to the identifier of the given storage system interface identifying the receiving storage system interface, the receiving storage system interface (i) provides a persistent discovery connection to the given host interface; and (ii) provides discovery information to the given host interface identifying a set of available storage system interfaces.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: February 18, 2025
    Assignee: Dell Products L.P.
    Inventors: Rivka Mayraz Matosevich, Ziv Dor
  • Patent number: 12223176
    Abstract: A technique is directed to managing wear leveling between storage devices. The technique includes generating a wear imbalance level indicating a variance between a first wear level of a first set of storage devices and a second wear level of a second set of storage devices. The technique further includes, after generating the wear imbalance level, performing a comparison operation that compares the wear imbalance level to a predefined imbalance threshold. The technique further includes, in response to the comparison operation indicating that the wear imbalance level is above the predefined imbalance threshold, providing the first set of storage devices as a first storage tier and the second set of storage devices as a second storage tier.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: February 11, 2025
    Assignee: Dell Products L.P.
    Inventors: Amitai Alkalay, Vamsi K. Vankamamidi, Lior Kamran
  • Patent number: 12210746
    Abstract: A tiered storage arrangement is contemplated that provides high speed tier 1 storage for rapid access to recalled data, mid-speed tier 2 storage for data that is not frequently recalled and tier 3 storage for archive purposes that may include tape library storage and even cold storage in vaults. Embodiments contemplate a server linked to all tiered storage devices on one end and a host computer on another. Data files can be migrated between the tiered storage systems based on migration policies, such as time elapsed from being filed or last accessed. Also, embodiments contemplate a time bar displayed at the host computer that provides accurate time predictions of data recall including information of the kind of storage on which a target file is stored and the pathway to recall the target file/s locally to the host computer.
    Type: Grant
    Filed: June 24, 2023
    Date of Patent: January 28, 2025
    Assignee: Spectra Logic Corporation
    Inventor: Nathan Christopher Thompson
  • Patent number: 12211548
    Abstract: Control logic in a memory device cause a programming pulse to be applied to a set of wordlines including a first set of even-numbered wordlines corresponding to a first set of memory cells to be erased and a second set of odd-numbered wordlines corresponding to a second set of memory cells to be erased, where a set of electrons are injected into a first set of gate regions, a second set of gate regions, and a set of inter-cell regions of a charge trap (CT) layer of the memory device. The control logic executes a first erase cycle on the first set of even-numbered wordlines to remove a first subset of electrons from the first set of gate regions corresponding to the first set of even-numbered wordlines. The control logic executes a second erase cycle on the second set of odd-numbered wordlines to remove a second subset of electrons from the second set of gate regions corresponding to the second set of even-numbered wordlines.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: January 28, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Hong-Yan Chen, Priya Vemparala Guruswamy, Pamela Castalino, Tomoko Ogura Iwasaki
  • Patent number: 12197792
    Abstract: In a storage system where Front-End (FE) tracks do not correspond to Back-End (BE) tracks on a one-to-one basis, a Logical Entry (LE) table is implemented in the BE processes to enable masking to occur on BE Logical Entry values rather than on BE tracks. An LE watch table is used to correlate LE values with BE tracks. When a RAID slice destage is initiated to move data from the FE tracks to BE tracks implementing the RAID slice, the LE watch table is used to identify a respective set of LE values that correspond to each respective RAID slice BE track. Entries of the BE mask corresponding to the LE values identified from the LE watch table are used to identify FE tracks that contain data to be included in the RAID slice destage. Metadata is retrieved for each identified FE track, and the RAID slice destage is implemented.
    Type: Grant
    Filed: January 1, 2024
    Date of Patent: January 14, 2025
    Assignee: Dell Products, L.P.
    Inventors: Lixin Pang, Rong Yu
  • Patent number: 12189486
    Abstract: A device that can efficiently manage capacity of a backup auxiliary storage device in an auxiliary storage device and a method of managing backup auxiliary storage device are disclosed. The auxiliary storage device includes an original auxiliary storage device, a backup auxiliary storage device, and a user input device. A controller that controls these devices is disclosed. The backup auxiliary storage device stores recovery information about the original auxiliary storage device. The user input device receives a user input for switching between a normal mode and a backup mode. When in the normal mode, the controller controls the auxiliary storage device so that a host computer boots using an OS in the original auxiliary storage device and is not able to access the backup auxiliary storage device.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: January 7, 2025
    Inventor: Deok Woo Kim
  • Patent number: 12189944
    Abstract: A solid-state storage device is provided that includes: a controller; non-volatile memory; a device interface; and a protocol-independent interface configured to couple to any one of a plurality of network adapters and communication ports so as to enable the controller to transmit data from the any one of the plurality of network adapters and communication ports. The controller is configured to receive data formatted according to a first protocol from an accessing device via the device interface. The protocol-independent interface includes a plurality of contacts coupled to the controller by a plurality of signal lines that enable data transmission from the controller to the protocol-independent interface. Each of the signal lines of the plurality of signal lines and each of the contacts of the plurality of contacts are configured to be enabled or disabled to form different channels through the protocol-independent interface to accommodate various target protocols.
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: January 7, 2025
    Assignee: SMART IOPS, INC.
    Inventors: Manuel Antonio d'Abreu, Ashutosh Kumar Das
  • Patent number: 12182401
    Abstract: The disclosure relates to a collecting method implemented by a first device including a first volatile memory, this first device interacting with a second device including a second non-volatile memory, the memories comprising objects each constituting an instance of an object-oriented language class. The method comprises an analysis of the objects by running through an object tree from the persistent roots; and on detecting that the analysis is finished, a collecting from the first and second memories for deleting each object that has not been analyzed during said analysis. This analysis in particular comprises, for each object: the identification of each reference pointing to another object; and the definition of a first or second type for each identified reference, this analysis continuing only along the references of the first type.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: December 31, 2024
    Assignee: IDEMIA IDENTITY & SECURITY FRANCE
    Inventors: Lauren Marjorie Del Giudice, Rëmi Louis Marie Duclos, Pierrick Bieules