Abstract: Stage task control blocks (TCB) are allocated for performing staging operations in a storage controller controlling one or more storage ranks. Destage TCBs are allocated for performing destaging operations in the storage controller. The storage controller adjusts how many stage TCBs and destage TCBs are to be allocated based on response times of the one or more storage ranks.

Abstract: Devices and techniques for storage class memory status are disclosed herein. A storage portion characteristics data structure is maintained. Here, the data structure includes an array of elements—where each element is sized to contain a reference to a storage portion in a storage class memory storage device, a first pointer to a first element in the array of elements, a second pointer to a second element in the array of elements, and a third pointer to a third element in the array of elements. The data structure includes a direction of pointer motion in which the second pointer precedes the third pointer and the first pointer precedes the second pointer with respect to the direction of pointer motion. A write request is performed to a storage portion reference retrieved from the first element. The first pointer is then advanced.

Abstract: Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules that are evaluated using the state of the NAND device. In some examples, the SLC cache migration process may utilize a number of NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data.

Abstract: A method and apparatus is disclosed for using supervised learning with closed loop feedback to improvement of output consistency for memory arrangements, such as a solid state drive.

Abstract: Techniques perform data synchronization. The techniques involve: in response to writing of data to a source storage array, determining whether a transmission link between the source storage array and a destination storage array is disconnected, the data being to be synchronized to the destination storage array; in response to determining that the transmission link is disconnected, accumulating in the source storage array the data written to the source storage array; in response to detecting that the transmission link is recovered, creating a snapshot for a storage unit associated with the data in the destination storage array; and in response to crashing of the source storage array during resynchronization of the data accumulated in the source storage array to the storage unit, restoring the storage unit in the destination storage array using the snapshot. Therefore, the storage space for the snapshot is greatly saved while disaster recovery is ensured.

Abstract: A method for improving I/O response times in a data replication environment is disclosed. In one embodiment, such a method includes receiving, at a primary storage system, a request to read data on the primary storage system. The method starts a timer upon receiving the request. In the event the data cannot be retrieved from the primary storage system by the time the timer expires, the method requests the data from a secondary storage system. In the event the primary storage system returns the data before the secondary storage system, the method returns data retrieved from the primary storage system to a host system. In the event the secondary storage system returns the data before the primary storage system, the method returns the data retrieved from the secondary storage system to the host system. A corresponding system and computer program product are also disclosed.

Abstract: Methods that can dynamically merge parity data for multiple data stripes are provided. One method includes detecting, by a processor, a disk failure in a redundant array of independent disks (RAID) configuration and, in response to detecting the disk failure, merging parity data stored in a plurality of sets of segments in a stripe of the RAID configuration to free space in a set of parity segments of the plurality of sets of segments. Systems and computer program products for performing the method are also provided.

Abstract: A system and method for offset protection data in a RAID array. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to store user data in a first page of a first storage device of the plurality of storage devices; generate intra-device protection data corresponding to the user data, and store the intra-device protection data at a first offset within the first page. The controller is further configured to generate inter-device protection data corresponding to the first page, and store the inter-device protection data at a second offset within a second page in a second storage device of the plurality of storage devices, wherein the first offset is different from the second offset.

Abstract: A system and method for offset protection data in a RAID array. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to store user data in a first page of a first storage device of the plurality of storage devices; generate intra-device protection data corresponding to the user data, and store the intra-device protection data at a first offset within the first page. The controller is further configured to generate inter-device protection data corresponding to the first page, and store the inter-device protection data at a second offset within a second page in a second storage device of the plurality of storage devices, wherein the first offset is different from the second offset.

Abstract: Embodiments of the present invention provide tightly coupled off-die memory along with an interface bus and smart buffer logic so as to efficiently perform certain frequent or repetitive operations off of a core logic. Embodiments of the present invention relieve the core logic from performing certain repetitive or frequent memory accesses and other operations so as to allow such core logic to perform other more general or varied operations. In this way, the universal interface bus, smart buffer logic, and off-die memory are specially configured to perform certain select frequent and repetitive operations while the core logic may configured to perform other operations so as to provide an improved configuration with increased computational capability and reduced power budget.

Abstract: A method for a virtual machine executed by a hypervisor includes identifying, for the virtual machine, mappings between a range of guest virtual addresses (GVAs) and a range of guest physical addresses (GPAs) that remain the same in an initial guest page table for a threshold period of time, creating an intermediate guest page table including one or more page table entries that map the range of the GVAs to a range of guest intermediate addresses (GIAs), and causing the GVA to be translated to a GIA using the intermediate guest page table in view of the one or more page table entries, where the translation is triggered responsive to a guest application of the virtual machine attempting to access a GVA in the range of the GVAs.

Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

Abstract: A method for recovering data for a file system includes a journal-less recovery process that detects one or more inconsistencies for file system blocks upon a system failure based on one or more comparisons of information for the file system blocks.

Abstract: The present application provides a method of randomly accessing a compressed structure in memory without the need for retrieving and decompressing the entire compressed structure.

Abstract: A system and method for reducing performance penalties of a host that is supplying a host memory buffer (HMB) for use by a storage device. The method may include modeling desired HMB access timing by the storage device in an initial offline analysis for multiple classes of workloads, periodically updating the access timing data stored in the storage device based on actual use and using the current HMB access timing information to modify storage device access to the HMB on the host. The system may include a storage device controller that quantifies different HMB access timing for different host workloads based on individual HMB regions.

Abstract: Techniques for utilizing flash storage as an extension of hard disk (HDD) storage are provided. In one embodiment, a computer system stores a subset of blocks of a logical file in a first physical file, associated with a first data structure that represents a filesystem object, on flash storage and a subset of blocks, associated with a second data structure that represents a filesystem object comprising tiering configuration information that includes an identifier of the first physical file, in a second physical file on HDD storage. The computer system processes an I/O request directed to the logical file by directing it to either the physical file on the flash storage or the HDD storage by verifying that the tiering configuration information exists in the data structure and determining whether the one or more blocks are part of the first subset of blocks or the second subset of blocks.

Abstract: A data storage device includes a nonvolatile memory device including memory block groups and map data blocks, each memory block group including a first page group storing data transmitted from a host device and a second page group storing address mapping information corresponding to the data; and a controller configured to determine whether the number of valid data stored in a first memory block group in which the second page group is damaged is equal to or smaller than a size of an available capacity of an open map data block which is being used, and control, when the number of the valid data is equal to or smaller than the available capacity, the nonvolatile memory device to store address mapping information corresponding to the valid data of the first memory block group, in the open map data block.

Abstract: An access request processing method and apparatus, and a computer device are disclosed. The computer device includes a processor, a dynamic random-access memory (DRAM), and a non-volatile memory (NVM). When receiving a write request, the processor may identify an object cache page according to the write request. The processor obtains the to-be-written data from a buffer according to a buffer pointer in the write request, the to-be-written data including a new data chunk to be written into the object cache page. The processor then inserts a new data node into a log chain of the object cache page, where the NVM stores data representing the log chain of the object cache page. The new data node includes information regarding the new data chunk of the object cache page. The computer device provided in this application can reduce system overheads while protecting data consistency.

Abstract: Devices and techniques for storage class memory status are disclosed herein. A storage portion characteristics data structure is maintained. Here, the data structure includes an array of elements—where each element is sized to contain a reference to a storage portion in a storage class memory storage device, a first pointer to a first element in the array of elements, a second pointer to a second element in the array of elements, and a third pointer to a third element in the array of elements. The data structure includes a direction of pointer motion in which the second pointer precedes the third pointer and the first pointer precedes the second pointer with respect to the direction of pointer motion. A write request is performed to a storage portion reference retrieved from the first element. The first pointer is then advanced.