Patents Examined by Cuong Q Nguyen
  • Patent number: 10411016
    Abstract: A semiconductor device includes a substrate, a plurality of lower electrodes disposed on the substrate and are repeatedly arranged in a first direction and in a second direction that crosses the first direction, and a first electrode support contacting a sidewall of at least one of the lower electrodes. The first electrode support includes a first support region including a first opening and a second support region disposed at a border of the first support region. An outer sidewall of the first electrode support includes a first sidewall extending in the first direction, a second sidewall extending in the second direction, and a connecting sidewall connecting the first and second sidewalls. The second support region includes the connecting sidewall. In a first portion of the second support region, a width of the first portion of the second support region decreases in a direction away from the first support region.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ye Ram Kim, Won Chul Lee
  • Patent number: 10410988
    Abstract: A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: September 10, 2019
    Assignee: Semtech Corporation
    Inventors: Kok Khoon Ho, Jonathan Clark, John MacLeod
  • Patent number: 10403792
    Abstract: Embodiments of the invention include a light emitting diode (LED) including a semiconductor structure. The semiconductor structure includes an active layer disposed between an n-type region and a p-type region. The active layer emits UV radiation. The LED is disposed on the mount. The mount is disposed on a conductive slug. A support surrounds the conductive slug. The support includes electrically conductive contact pads disposed on a bottom surface, and a thermally conductive pad disposed beneath the conductive slug, wherein the thermally conductive pad is not electrically connected to the LED.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: September 3, 2019
    Assignee: RayVio Corporation
    Inventors: Saijin Liu, Li Zhang, Douglas A. Collins
  • Patent number: 10403790
    Abstract: A semiconductor light-emitting device includes a light-emitting member that includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light-emitting layer between the first semiconductor layer and the second semiconductor layer, a first metal layer electrically connected to the first semiconductor layer, and a second metal layer electrically connected to the second semiconductor layer. The light-emitting member has a first surface including a front surface of the first semiconductor layer, a second surface including a front surface of the second semiconductor layer, a side surface including an outer periphery of the first semiconductor layer, and a recess extending inwardly of the second surface to an interior portion of the first semiconductor layer to expose an inner surface on a side of the recess facing the side surface.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: September 3, 2019
    Assignee: ALPAD CORPORATION
    Inventors: Hiroshi Katsuno, Masakazu Sawano, Kazuyuki Miyabe
  • Patent number: 10395994
    Abstract: A method for fabricating a semiconductor device having a uniform spacer thickness between field-effect transistors (FETs) associated with regions of the device is provided. A first semiconductor material is epitaxially grown in a first source/drain region within a first region of the device associated with a first FET. A capping layer is selectively formed on the first semiconductor material by forming a layer over the first and second regions that reacts with the first semiconductor material to form the capping layer. A second semiconductor material is epitaxially grown in a second source/drain region within a second region of the device associated with a second FET. The capping layer caps the growth of the first semiconductor material during the epitaxial growth of the second semiconductor material to provide the uniform spacer thickness between the first and second FETs.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Heng Wu, Juntao Li, Peng Xu, Kangguo Cheng, Choonghyun Lee
  • Patent number: 10388736
    Abstract: In an embodiment, a method includes forming an intentionally doped superlattice laminate on a support substrate, forming a Group III nitride-based device having a heterojunction on the superlattice laminate layer, and forming a charge blocking layer between the heterojunction and the superlattice laminate.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 20, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Horst Schäfer, Oliver Häberlen
  • Patent number: 10381385
    Abstract: An object of the present invention is to decrease substantial resistance of an electrode such as a transparent electrode or a wiring, and furthermore, to provide a display device for which is possible to apply same voltage to light-emitting elements. In the invention, a auxiliary wiring that is formed in one layer in which a conductive film of a semiconductor element such as an electrode, wiring, a signal line, a scanning line, or a power supply line is connected to an electrode typified by a second electrode, and a wiring. It is preferable that the auxiliary wiring is formed into a conductive film to include low resistive material, especially, formed to include lower resistive material than the resistance of an electrode and a wiring that is required to reduce the resistance.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: August 13, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Noriko Miyagi, Masayuki Sakakura, Tatsuya Arao, Ritsuko Nagao, Yoshifumi Tanada
  • Patent number: 10374037
    Abstract: A semiconductor junction may include a first semiconductor material and a second material. The first and the second semiconductor materials are extrinsically undoped. At least a portion of a valence band of the second material has a higher energy level than at least a portion of the conduction band of the first semiconductor material (type-III band alignment). A flow of a majority of free carriers across the semiconductor junction is diffusive. A region of generation and/or recombination of a plurality of free carriers is confined to a two-dimensional surface of the second material, and at the interface of the first semiconductor material and the second material.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: August 6, 2019
    Assignee: THE UNIVERSITY OF NORTH CAROLINA AT CHARLOTTE
    Inventors: Raphael Tsu, Ian T. Ferguson, Nikolaus Dietz
  • Patent number: 10373938
    Abstract: A light-emitting element provides a substrate; a plurality of light-emitting cells arranged on the substrate and spaced apart from each other; a connection wire configured to electrically interconnect the light-emitting cells; a first bonding pad electrically connected to the second conductive semiconductor layer of a first light-emitting cell among the light-emitting cells; and a second bonding pad electrically connected to the first conductive semiconductor layer of a second light-emitting cell among the light-emitting cells, wherein a boundary area includes a first boundary disposed between the light-emitting cells adjacent to each other in a first direction among the plurality of light-emitting, and wherein all of the first boundary areas are spaced apart from each other in the first direction.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: August 6, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Yong Nam Park
  • Patent number: 10373909
    Abstract: Semiconductor structures including copper interconnect structures and methods include selective surface modification of copper by providing a CuxTiyNz alloy in the surface. The methods generally include forming a titanium nitride layer on an exposed copper surface followed by annealing to form the CuxTiyNz, alloy in the exposed copper surface. Subsequently, the titanium layer is removed by a selective wet etching.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Raghuveer R. Patlolla, Cornelius Brown Peethala, Roger A. Quon, Chih-Chao Yang
  • Patent number: 10361178
    Abstract: In an embodiment, an interconnection structure includes a first semiconductor device including a conductive stud, a second device including a contact pad, an adhesive layer including an organic component arranged between a distal end of the conductive stud and the contact pad, the adhesive layer coupling the conductive stud to the contact pad, and a conductive layer extending from the conductive stud to the contact pad. The conductive layer has a melting point of at least 600° C.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: July 23, 2019
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Standing
  • Patent number: 10361222
    Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formulation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: July 23, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Shunpei Yamazaki, Koji Dairiki, Hiroshi Shibata, Chiho Kokubo, Tatsuya Arao, Masahiko Hayakawa, Hidekazu Miyairi, Akihisa Shimomura, Koichiro Tanaka, Mai Akiba
  • Patent number: 10355151
    Abstract: A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent photodiodes formed in the substrate. Each photodiode may include a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the second conductivity type, and a second well within the retrograde well having the first conductivity type. Each photodiode may further include first and second superlattices respectively overlying each of the first and second wells. Each of the first and second superlattices may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: July 16, 2019
    Assignee: ATOMERA INCORPORATED
    Inventors: Yi-Ann Chen, Abid Husain, Hideki Takeuchi
  • Patent number: 10347584
    Abstract: A fan-out semiconductor package includes: a core member having a through-hole and having first fiducial marks disposed on an upper surface thereof in the vicinity of the through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads and second fiducial marks disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip, wherein the first fiducial marks are disposed to be symmetrical to each other with respect to a center of the through-hole on a plane view, and the second fiducial marks are disposed to be symmetrical to each other with respect to a center of the semiconductor chip on the plane view.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: July 9, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Kyu Il Hwang
  • Patent number: 10347588
    Abstract: After forming a first electromagnetic radiation blocking layer over a front side of a device wafer, the device wafer is bonded to a handle substrate from the front side. A semiconductor substrate in the device wafer is thinned from its backside. Trenches are formed extending through the device wafer and the first electromagnetic radiation blocking layer such that the device wafer is singulated into semiconductor dies. A second electromagnetic radiation blocking layer portion is formed on a backside surface of and sidewalls surfaces of each of the semiconductor dies such that each of the semiconductor dies are fully encapsulated by the first and second electromagnetic radiation blocking layer portions.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: July 9, 2019
    Assignees: International Business Machines Corporation, JOHNSON & JOHNSON VISION CARE, INC.
    Inventors: Paul S. Andry, Cornelia K. Tsang, Adam Toner
  • Patent number: 10340184
    Abstract: A method for producing a semiconductor device includes depositing a first oxide insulating film containing an impurity of a first conductivity type on a fourth first-conductivity-type semiconductor layer formed on a substrate; depositing a sixth insulating nitride film; depositing a second oxide insulating film containing an impurity of the first conductivity type; depositing a seventh insulating nitride film; depositing a third oxide insulating film containing an impurity of the first conductivity type; etching the first insulating film, the sixth insulating film, the second insulating film, and the seventh insulating film to form a contact hole; forming a first pillar-shaped silicon layer in the contact hole by epitaxial growth; removing the sixth insulating film and the seventh insulating film; forming a first gate and a second gate; and forming a contact connecting the first gate and the second gate.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 2, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10340410
    Abstract: The present invention relates to an optocoupler including a light source having a body and electrical leads, a light detector having a diode stack a metal end cap and electrical leads, and an optical cavity including optically transparent material at least partially covering the body of the light source and the diode stack of the light detector. Also included is a reflective layer including optically reflective material surrounding the optical cavity. The electrical leads of the light source, the metal end cap and the electrical leads of the light detector protrude from the optical cavity and the reflective layer.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: July 2, 2019
    Assignee: HARRIS CORPORATION
    Inventors: Stuart D. Wood, Steven M. DeSmitt, Eugene G. Olczak
  • Patent number: 10333044
    Abstract: Phononic metamaterials and methods for reducing the group velocities and the thermal conductivity in at least partially crystalline base material are provided, such as for thermoelectric energy conversion. In one implementation, a method for reducing thermal conductivity through an at least partially crystalline base material is provided. In another implementation, a phononic metamaterial structure is provided. The phononic metamaterial structure in this implementation includes: an at least partially crystalline base material configured to allow a plurality of phonons to move to provide thermal conduction through the base material; and at least one material coupled (e.g., as an inclusion, extending substructure, outer matrix, a coating to heavy inner inclusion, etc.) to the at least partially crystalline base material via at least one relatively compliant or soft material (e.g., graphite, rubber or polymer).
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: June 25, 2019
    Assignee: The Regents of the University of Colorado, a body corporate
    Inventor: Mahmoud I. Hussein
  • Patent number: 10326016
    Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, and a buried region. A channel junction is formed between the body region and the high voltage well. The buried region is formed in the substrate and the epitaxial layer, and in a vertical direction, a part of the buried region is located in the substrate and another part of the buried region is located in the epitaxial layer. In the channel direction, an inner side boundary of the buried region is between the drain and the channel junction. An impurity concentration of a second conductive type of the buried region is sufficient to prevent the high voltage well between the channel junction and the drain from being completely depleted when the high-side power device operates in a conductive operation. A corresponding manufacturing method is also disclosed.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: June 18, 2019
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • Patent number: 10324344
    Abstract: A liquid crystal display panel and its driving circuit, manufacturing method are disclosed. The driving circuit has a first switching element. The first terminal of the first switching element is connected to one data line of the liquid crystal display panel. At the array manufacturing process stage, the control terminal of the first switching element is input a first reference voltage. The second terminal of the first switching element is connected to a first discharge circuit. During the stage to drive the liquid crystal display panel to display or to test the liquid crystal display panel, the control terminal of the first switching element is input a first control signal. The second terminal of the first switching element is input a data signal. By the aforementioned ways, it can simultaneously achieve an ESD protection and to save the panel space to be favorable for narrow frame design.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: June 18, 2019
    Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd., Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventors: Cong Wang, Peng Du