Patents Examined by Cuong Q Nguyen
  • Patent number: 10811480
    Abstract: An organic light emitting display (OLED) device includes a substrate, a semiconductor element on the substrate, a planarization layer on the semiconductor, and a light emitting structure on the planarization layer. The planarization layer includes a contact hole exposing a portion of the semiconductor and a plurality of grooves surrounding the contact hole. The light emitting structure is electrically connected to the semiconductor element via the contact hole.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Eonjoo Lee, Jin-Whan Jung, Hyoeng-Ki Kim, Junhyuk Woo
  • Patent number: 10811535
    Abstract: An SGT production method includes a first step of forming a fin-shaped semiconductor layer and a first insulating film; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and etching the third insulating film, the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, subjecting the second polysilicon to etch back to expose the first hard mask, depositing a sixth insulating film, etching the sixth insulating film to form a second hard mask on a side wall of the first hard mask, and etching the second polysilicon to form a second dummy gate.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: October 20, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10804362
    Abstract: In a first aspect of a present inventive subject matter, a crystalline oxide semiconductor film includes a crystalline oxide semiconductor that contains a corundum structure as a major component, a dopant, and an electron mobility that is 30 cm2/Vs or more.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 13, 2020
    Assignee: FLOSFIA INC.
    Inventors: Rie Tokuda, Masaya Oda, Toshimi Hitora
  • Patent number: 10804397
    Abstract: An SGT production method includes a first step of forming a fin-shaped semiconductor layer and a first insulating film; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and etching the third insulating film, the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, subjecting the second polysilicon to etch back to expose the first hard mask, depositing a sixth insulating film, etching the sixth insulating film to form a second hard mask on a side wall of the first hard mask, and etching the second polysilicon to form a second dummy gate.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: October 13, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10797211
    Abstract: A method of manufacturing support elements for lighting devices includes: providing an elongated, electrically non-conductive substrate with opposed surfaces, with an electrically-conductive layer extending along one of said opposed surfaces, etching said electrically-conductive layer to provide a set of electrically-conductive tracks extending along the non-conductive substrate with at least one portion of the non-conductive substrate left free by the set of electrically-conductive tracks, forming a network of electrically-conductive lines coupleable with at least one light radiation source at said portion of said non-conductive substrate left free by the electrically-conductive tracks. Said forming operation includes selectively removing e.g. via laser etching a further electrically-conductive layer provided on said non-conductive substrate, or printing electrically-conductive material onto the non-conductive substrate.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 6, 2020
    Assignee: OSRAM GMBH
    Inventors: Lorenzo Baldo, Alessio Griffoni, Federico Poggi
  • Patent number: 10796931
    Abstract: A manufacturing method of a package structure is described. The method includes at least the following steps. A carrier is provided. A semiconductor die and a sacrificial structure are disposed on the carrier. The semiconductor die is electrically connected to the bonding pads on the sacrificial structure through a plurality of conductive wires. As encapsulant is formed on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires. The carrier is debonded, and at least a portion of the sacrificial structure is removed through a thinning process. A redistribution layer is formed on the semiconductor die and the encapsulant. The redistribution layer is electrically connected to the semiconductor die through the conductive wires.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: October 6, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Han-Wen Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien, Nan-Chun Lin
  • Patent number: 10796996
    Abstract: A semiconductor device includes a substrate, a dielectric layer disposed on the substrate, and a conductive stack disposed within the dielectric layer. The conductive stack includes at least one first conductive layer, a second conductive layer disposed over the at least one first conductive layer, and a contact structure disposed between the at least one first conductive layer and the second conductive layer. The contact structure includes a contact via electrically connecting the at least one first conductive layer to the second conductive layer, and a glue layer conformal to sidewalls and a bottom surface of the contact via. The glue layer has isolated lattices and an amorphous region at which the isolated lattices are uniformly distributed.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Ming Lu, Jung-Chih Tsao, Yao-Hsiang Liang, Chih-Chang Huang, Han-Chieh Huang
  • Patent number: 10797148
    Abstract: In a method of forming a Group III-V semiconductor layer on a Si substrate, a first source gas containing a Group V element is supplied to a surface of the Si substrate while heating the substrate at a first temperature, thereby terminating the Si surface with the Group V element. Then, a second source gas containing a Group III element is supplied to the surface while heating the substrate at a second temperature, thereby forming a nucleation layer directly on the surface of the Si substrate. After the nucleation layer is formed, the supply of the second source gas is stopped and the substrate is annealed at a third temperature while the first source gas being supplied, thereby forming a seed layer. After the annealing, the second source gas is supplied while heating the substrate at a fourth temperature, thereby forming a body III-V layer semiconductor on the seed layer.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mark Van Dal, Matthias Passlack, Martin Christopher Holland
  • Patent number: 10797084
    Abstract: A display apparatus is provided that includes a substrate having a display area and a peripheral area located outside the display area. A first part of an edge of the display area has a round shape and the peripheral area includes a pad area. The display apparatus further includes a first wiring extending in a direction toward the first part from the pad area, and having a first discontinuous point at which the first wiring is physically discontinuous; and a first bridge wiring allowing the first wiring to be electrically continuous at the first discontinuous point.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: October 6, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Wonse Lee, Yunkyeong In, Kwangmin Kim, Joongsoo Moon, Ae Shin, Jieun Lee
  • Patent number: 10777740
    Abstract: A semiconductor integrated circuit device and a fabrication method thereof are disclosed. The resistive memory device includes a lower electrode, a resistive layer formed in a resistance change region on the lower electrode, an upper electrode formed on the resistive layer, and an insertion layer configured to allow a reset current path of the resistive layer, which is formed from the upper electrode to the lower electrode, to be bypassed in a direction perpendicular to or parallel to a surface of the lower electrode.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventors: Dong Yean Oh, Chang Soo Woo
  • Patent number: 10777635
    Abstract: Embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device, and relate to the field of display technology. The contact area between a first conductive pattern and a second conductive pattern may be increased. The display substrate includes a display area and a peripheral area surrounding the display area. The peripheral area includes a first conductive pattern including at least two first hollow areas as alignment marks, an insulation layer disposed on the first conductive pattern, the insulation layer including a first insulating pattern, the first insulating pattern covering the first hollow area, and the first insulating pattern being incompletely covering space between adjacent first hollow areas, a second conductive pattern disposed on the insulating layer, the second conductive pattern penetrating through the hollow area on the first insulating pattern and electrically connected to the first conductive pattern.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: September 15, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Fan Yang, Kun Guo, Jie Pu
  • Patent number: 10777634
    Abstract: An organic light-emitting display apparatus includes a substrate, pixels, a pixel defining layer (PDL), a first via layer, a second via layer, first lines, and a second line. The pixels are arranged on the substrate in a first direction (D1) and a second direction (D2) intersecting one another, and include organic light-emitting diodes (OLEDs). The OLEDs include pixel electrodes (PEs). The PDL covers edges of the PEs and defines light-emitting regions via openings partially exposing the PEs. The first and second via layers are between the PEs and the substrate. The first lines extend in the D2 between the first via layer and the substrate. The second line is between the second and first via layers. The second line at least partially extends around the light-emitting regions. The second line contacts the first lines through via holes. Each via hole is provided every two pixels arranged in the D2.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: September 15, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jisu Na, Youngjin Cho, Yangwan Kim, Joongsoo Moon, Keunsoo Lee
  • Patent number: 10770553
    Abstract: In a first aspect of a present inventive subject matter, a layered structure includes a first semiconductor layer containing as a major component an ?-phase oxide semiconductor crystal; and a second semiconductor layer positioned on the first semiconductor layer and containing as a major component an oxide semiconductor crystal with a tetragonal crystal structure.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 8, 2020
    Assignee: FLOSFIA INC.
    Inventors: Tokiyoshi Matsuda, Takashi Shinohe, Shingo Yagyu, Takuto Igawa
  • Patent number: 10770579
    Abstract: An n-type drift region, a p-type first body region and a p-type contact region are formed on an SiC substrate by epitaxial growth. An opening is formed within the contact region by etching such that the first body region is exposed through the opening, and a p-type second body region is formed on the first body region exposed through the opening by epitaxial growth. An n-type source region is formed by epitaxial growth, and an opening is formed within a part of the source region located on the contact region by etching such that the contact region is exposed through the opening. A trench is formed by etching such that the trench extends from the source region to the drift region through the opening of the contact region, and a gate insulating film and a gate electrode are formed within the trench.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: September 8, 2020
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hidefumi Takaya, Yasushi Urakami, Yukihiko Watanabe
  • Patent number: 10770440
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a micro-light emitting diode (LED) display assembly and methods of manufacture. The structure includes an interposer and a plurality of micro-LED arrays each of which include a plurality of through-vias connecting pixels of the plurality of micro-LED arrays to the interposer.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: September 8, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Luke England, Bartlomiej Jan Pawlak
  • Patent number: 10771024
    Abstract: One aspect of this disclosure is a power amplifier module that includes a power amplifier on a substrate and a semiconductor resistor on the substrate. The power amplifier includes a bipolar transistor having a collector, a base, and an emitter. The collector has a doping concentration of at least 3×1016 cm?3 at an interface with the base. The collector also has at least a first grading in which doping concentration increases away from the base. The semiconductor resistor includes a resistive layer that that includes the same material as a layer of the bipolar transistor. Other embodiments of the module are provided along with related methods and components thereof.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: September 8, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Peter J. Zampardi, Jr., Hongxiao Shao, Tin Myint Ko, Matthew Thomas Ozalas, David Steven Ripley, Philip John Lehtola
  • Patent number: 10763396
    Abstract: A light-emitting module and a display device including the same are disclosed. In an embodiment a light-emitting module includes a plurality of emission regions configured to emit light, at least one first emission region and at least one second emission region of a first type configured to emit light of a first color locus and at least one first emission region and at least one second emission region of a second type configured to emit light of a second color locus and a control device for supplying the emission regions with current, wherein the emission regions are arranged on a common semiconductor chip, wherein the first color locus is different from the second color locus, wherein the first and second emission regions of the first type are adjacent to one another, and wherein the first and second emission regions of the second type are adjacent to one another.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: September 1, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Jürgen Moosburger, Matthias Sabathil, Frank Singer
  • Patent number: 10756291
    Abstract: The embodiments of the disclosure provides a method of manufacturing an OLED panel and an OLED panel. The method includes: forming an anode electrode connected to a source electrode of a TFT and a bridge electrode connected to an auxiliary electrode on a TFT substrate; forming a plurality of metal protrusions on the bridge electrode, the surfaces of the metal protrusions having a plurality of corners; sequentially forming an electron transport layer, an electron injection layer and a cathode electrode on the bridge electrode and the metal protrusions; and applying a voltage on the auxiliary electrode or the bridge electrode to burn a portion of the electron transport layer and a portion of the electron injection layer corresponding to the corners of the metal protrusions to connect the cathode electrode and the auxiliary electrode.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: August 25, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Liangfen Zhang, Xiaoxing Zhang, Jangsoon Im
  • Patent number: 10748859
    Abstract: A power converting device such that an overcurrent is interrupted and damage to a power semiconductor element can be prevented is obtained. The power converting device includes a power semiconductor element, a wiring member connected to an electrode of the power semiconductor element, a bus bar that supplies power to the power semiconductor element, and a frame that houses the power semiconductor element, wherein the bus bar has a connection terminal connected to the wiring member, and a fuse portion is provided in the connection terminal.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: August 18, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenta Fujii, Yuji Shirakata, Masahiro Ueno, Tomoaki Shimano
  • Patent number: 10748943
    Abstract: A display device includes: a substrate; first and second transistors provided on the substrate to be spaced apart from each other, the first and second transistors being electrically connected to each other; and a display unit electrically connected to the first transistor, wherein the first transistor includes a first semiconductor layer including crystalline silicon, a first gate electrode, a first source electrode, and a first drain electrode, wherein the second transistor includes a second semiconductor layer including an oxide semiconductor, a second gate electrode, a second source electrode, and a second drain electrode, wherein each of the second source electrode and the second drain electrode includes a first layer that includes molybdenum and is provided on the second semiconductor layer, a second layer that includes aluminum and is provided on the first layer, and a third layer that includes titanium and is provided on the second layer.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyun Min Cho, Shin Il Choi, Kyeong Su Ko, Sang Gab Kim, Joon Geol Lee