Patents Examined by Cuong Q Nguyen
  • Patent number: 11145601
    Abstract: A semiconductor chip including an alignment pattern is provided. The semiconductor chip includes a substrate associated with a main chip region of a semiconductor wafer and including a scribe lane. A lower interlayer insulating layer is disposed on the substrate, a low-K layer including dummy metal patterns is disposed on the lower interlayer insulating layer, an alignment pattern is disposed on the low-K layer, and a passivation layer covers the alignment pattern.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: October 12, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon Sung Kim, Yun Hee Kim, Byung Moon Bae, Hyun Su Sim, Jun Ho Yoon, Jung Ho Choi
  • Patent number: 11145605
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate and a first crack-detecting structure positioned in the substrate and comprising a first capacitor unit. The first capacitor unit comprises a first bottom conductive layer positioned in the substrate, a first capacitor insulating layer surrounding the first bottom conductive layer, and a first buried plate surrounding the first capacitor insulating layer.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: October 12, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jar-Ming Ho
  • Patent number: 11139264
    Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Ji Yong Park, Kyu Oh Lee
  • Patent number: 11133400
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Kuo-Hui Chang, Yi-Cheng Chao
  • Patent number: 11127909
    Abstract: The present technology relates to a photoelectric conversion element, a measuring method of the same, a solid-state imaging device, an electronic device, and a solar cell capable of further improving a quantum efficiency in a photoelectric conversion element using a photoelectric conversion layer including an organic semiconductor material. The photoelectric conversion element includes two electrodes forming a positive electrode (11) and a negative electrode (14), at least one charge blocking layer (13, 15) arranged between the two electrodes, and a photoelectric conversion layer (12) arranged between the two electrodes. The at least one charge blocking layer is an electron blocking layer (13) or a hole blocking layer (15), and a potential of the charge blocking layer is bent. The present technology is applied to, for example, a solid-state imaging device, a solar cell, and the like having a photoelectric conversion element.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: September 21, 2021
    Assignee: SONY CORPORATION
    Inventors: Yukio Kaneda, Ryoji Arai, Toshiki Moriwaki
  • Patent number: 11121190
    Abstract: Provided is an optoelectronic device comprising an optoelectronic element and circuitry connected to the optoelectronic element, wherein the optoelectronic element comprises plural quantum dots or plural nanorods, and wherein the circuitry is configured to be capable of switching the optoelectronic element between a configuration in which the circuitry provides an effective forward bias voltage that causes the optoelectronic element to emit light and a configuration in which the circuitry provides an effective reverse bias voltage that causes the optoelectronic element to be capable of generating a photocurrent when light to which the optoelectronic element is sensitive strikes the optoelectronic element.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: September 14, 2021
    Assignees: Dow Global Technologies LLC, Rohm and Haas Company, The Board of Trustees of the University of Illinois, Rohm and Haas Electronic Materials LLC
    Inventors: Peter Trefonas, III, Kishori Deshpande, Trevor Ewers, Edward Greer, Jaebum Joo, Bong Hoon Kim, Nuri Oh, Jong Keun Park, Moonsub Shim, Jieqian Zhang
  • Patent number: 11121032
    Abstract: A method of forming an active device having self-aligned source/drain contacts and gate contacts, including, forming an active area on a substrate, where the active area includes a device channel; forming two or more gate structures on the device channel; forming a plurality of source/drains on the active area adjacent to the two or more gate structures and device channel; forming a protective layer on the surfaces of the two or more gate structures, plurality of source/drains, and active layer; forming an interlayer dielectric layer on the protective layer; removing a portion of the interlayer dielectric and protective layer to form openings, where each opening exposes a portion of one of the plurality of source/drains; forming a source/drain contact liner in at least one of the plurality of openings; and forming a source/drain contact fill on the source/drain contact liner.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 11121166
    Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate including a front surface, a back surface opposite to the front surface, and a light-sensing region extending from the front surface into the semiconductor substrate. The image sensor device includes a light-blocking structure in the semiconductor substrate and surrounding the light-sensing region. The light-blocking structure includes a conductive light reflection structure and a light absorption structure, and the light absorption structure is between the conductive light reflection structure and the back surface. The image sensor device includes an insulating layer between the light-blocking structure and the semiconductor substrate.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Volume Chien, Yun-Wei Cheng, Zhe-Ju Liu, Kuo-Cheng Lee, Chi-Cherng Jeng, Chuan-Pu Liu
  • Patent number: 11114468
    Abstract: A thin film transistor (TFT) array substrate is provided. The TFT array substrate includes a display device plate and a semiconductor layer disposed on the display device plate. A thickness of the semiconductor layer is less than or equal to 35 nm.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: September 7, 2021
    Inventors: Xin Zhang, Lisheng Li, Peng He
  • Patent number: 11114592
    Abstract: A light emitting assembly comprising a solid state device, when and if coupleable with a power supply constructed and arranged to power the solid state device to emit from the solid state device a first wavelength radiation, and an enveloping vessel enhancing the luminescence of the solid-state device and providing a mechanism for arranging luminophoric medium in receiving relationship to said first, radiation, and which in exposure to said first radiation, is excited to responsively emit second wavelength radiation or to otherwise transfer its energy without radiation to a third radiative component. In a specific embodiment, monochromatic blue or UV light output from a light-emitting diode is converted to achromatic light without hue by packaging the diode with fluorescent organic and/or inorganic fluorescers and phosphors on the walls of the solid-state light envelope which keeps the diode and the fluorescers and phosphors under a vacuum or a rare or Noble gas.
    Type: Grant
    Filed: March 6, 2021
    Date of Patent: September 7, 2021
    Inventor: Bruce H. Baretz
  • Patent number: 11114593
    Abstract: This disclosure describes optoelectronic modules, methods for manufacturing pluralities of discrete optoelectronic modules, and optoelectronic molding tools. The methods include coating a substrate wafer and a plurality of optoelectronic components with a photosensitive material, and further include exposing select portions of the photosensitive material to electromagnetic radiation. The exposed portions delineate at least in part the dimensions of the optical channels, wherein the optical channels are associated with at least one optoelectronic component. In some instances, optical elements are incorporated into the optical channels. In some instances, the exposed portions are the optical channels. In some instances, the exposed portions are spacers between the optical channels.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: September 7, 2021
    Assignee: ams Sensors Singapore Pte. Ltd.
    Inventors: Robert Lenart, Sonja Gantner, Oezkan Ahishali
  • Patent number: 11114611
    Abstract: A method to make magnetic random access memory with small footprint using O-ion implantation to form electrically isolated memory pillar and electric (bottom and top) leads, which are made from some oxygen gettering materials, Mg, Zr, Y, Th, Ti, Al, Ba. The doped O-ions react with metal atoms to form fully oxidized metal oxide after high temperature anneal. The method only needs two photolithography patterning and oxygen implantations and no etch and dielectric refill are needed, thus significantly reduce process cost. The method can produce extremely small MRAM cell size with perfectly vertical pillar edges (FIG. 1).
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: September 7, 2021
    Inventor: Yimin Guo
  • Patent number: 11107845
    Abstract: A Thin Film Transistor (TFT) substrate includes a first semiconductor film, a first electrically conductive member provided in a layer higher than the first semiconductor film, an interlayer insulating film provided in a layer higher than the first electrically conductive member and including a first through hole, a second semiconductor film provided in a layer higher than the interlayer insulating film, a second electrically conductive member provided in a layer higher than the second semiconductor film, an organic insulating film provided in a layer higher than the second electrically conductive member and including a second through hole, and a third electrically conductive member provided in a layer higher than the organic insulating film. A contact hole extends through the first and the second through hole to the first electrically conductive member.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 31, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Yaneda
  • Patent number: 11107700
    Abstract: A method of fabricating a semiconductor package may include forming a lower re-distribution layer, forming a stack, bonding the stack to a portion of the lower re-distribution layer, stacking a semiconductor chip on a top surface of the lower re-distribution layer, and forming an upper re-distribution layer on the semiconductor chip and the stack.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: August 31, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kyoung Lim Suk
  • Patent number: 11100857
    Abstract: [Object] To provide a display device that displays a display image with high resolution and higher uniformity, and an electronic apparatus including the display device. [Solution] A display device including: a driving transistor including a first-conductivity-type activation region provided in a semiconductor substrate, an opening provided to cross the activation region, a gate insulating film provided on the activation region including an inside of the opening, a gate electrode filling the opening, and second-conductivity-type diffusion regions provided on both sides of the activation region across the opening; and an organic electroluminescent element configured to be driven by the driving transistor.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: August 24, 2021
    Assignee: Sony Corporation
    Inventor: Shimpei Tsujikawa
  • Patent number: 11092836
    Abstract: The present invention discloses an array substrate, including: a first metal layer, a second metal layer and a common electrode layer which are insulated from each other and sequentially formed on a base substrate; the first metal layer includes a gate line, the second metal layer includes a data line, and the common electrode layer includes a touch sensing electrode; the second metal layer includes a touch signal line, the touch signal line is electrically connected to the touch sensing electrode, and the touch signal line and the data line are intersected each other and are disconnected at an intersection location; and the first metal layer includes a bridging connection line, two ends of the bridging connection line are connected to the touch signal line such that the touch signal line disconnected at the intersection location are electrically connected. A manufacturing method and an in-cell touch panel are also disclosed.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: August 17, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Pengfei Yu, Jiawei Zhang
  • Patent number: 11094728
    Abstract: The present technology relates to an image pickup device and an electronic apparatus that are configured to enhance characteristics. A solid-state image pickup device includes a photoelectric conversion section that is arranged on a semiconductor substrate and configured to photoelectrically convert an incident light, a moth-eye section that includes recesses and projections formed on a surface on a light incident side in the semiconductor substrate and has, when a cross section approximately parallel to a direction toward the photoelectric conversion section from the light incident side is viewed, a recessed portion protruding toward the side of the photoelectric conversion section, the recessed portion having a curvature or a polygonal shape, and a region that is arranged adjacent to and opposite to the photoelectric conversion section of the moth-eye section and has a refractive index different from a refractive index of the semiconductor substrate.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: August 17, 2021
    Assignee: SONY CORPORATION
    Inventors: Satoe Miyata, Itaru Oshiyama
  • Patent number: 11088177
    Abstract: The invention provides an array substrate and manufacturing method thereof.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: August 10, 2021
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Liwang Song, Zhaohui Li
  • Patent number: 11088280
    Abstract: The disclosure provides for a transistor which may include: a gate stack on a substrate, the gate stack including a gate dielectric and a gate electrode over the gate dielectric; a channel within the substrate and under the gate stack; a doped source and a doped drain on opposing sides of the channel, the doped source and the doped drain each including a dopant, wherein the dopant and the channel together have a first coefficient of diffusion and the doped source and the doped drain each have a second coefficient of diffusion; and a doped extension layer separating each of the doped source and the doped drain from the channel, the doped extension layer having a third coefficient of diffusion, wherein the third coefficient of diffusion is greater than the first coefficient of diffusion and the second coefficient of diffusion is less than the third coefficient of diffusion.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: August 10, 2021
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Nicolas L. Breil, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 11081578
    Abstract: We disclose herein a depletion mode III-nitride semiconductor based heterojunction device, comprising: a substrate; a III-nitride semiconductor region formed over the substrate, wherein the III-nitride semiconductor region comprises a heterojunction comprising at least one two-dimensional carrier gas of second conductivity type; a first terminal operatively connected to the III-nitride semiconductor region; a second terminal laterally spaced from the first terminal in a first dimension and operatively connected to the III-nitride semiconductor region; at least two highly doped semiconductor regions of a first conductivity type formed over the III-nitride semiconductor region, the at least two highly doped semiconductor regions being formed between the first terminal and the second terminal; and a gate terminal formed over the at least two highly doped semiconductor regions; wherein the at least two highly doped semiconductor regions are spaced from each other in a second dimension.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: August 3, 2021
    Assignee: CAMBRIDGE GAN DEVICES LIMITED
    Inventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi, Martin Arnold