Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formulation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.

Abstract: A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent photodiodes formed in the substrate. Each photodiode may include a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the second conductivity type, and a second well within the retrograde well having the first conductivity type. Each photodiode may further include first and second superlattices respectively overlying each of the first and second wells. Each of the first and second superlattices may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: After forming a first electromagnetic radiation blocking layer over a front side of a device wafer, the device wafer is bonded to a handle substrate from the front side. A semiconductor substrate in the device wafer is thinned from its backside. Trenches are formed extending through the device wafer and the first electromagnetic radiation blocking layer such that the device wafer is singulated into semiconductor dies. A second electromagnetic radiation blocking layer portion is formed on a backside surface of and sidewalls surfaces of each of the semiconductor dies such that each of the semiconductor dies are fully encapsulated by the first and second electromagnetic radiation blocking layer portions.

Abstract: A fan-out semiconductor package includes: a core member having a through-hole and having first fiducial marks disposed on an upper surface thereof in the vicinity of the through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads and second fiducial marks disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip, wherein the first fiducial marks are disposed to be symmetrical to each other with respect to a center of the through-hole on a plane view, and the second fiducial marks are disposed to be symmetrical to each other with respect to a center of the semiconductor chip on the plane view.

Abstract: The present invention relates to an optocoupler including a light source having a body and electrical leads, a light detector having a diode stack a metal end cap and electrical leads, and an optical cavity including optically transparent material at least partially covering the body of the light source and the diode stack of the light detector. Also included is a reflective layer including optically reflective material surrounding the optical cavity. The electrical leads of the light source, the metal end cap and the electrical leads of the light detector protrude from the optical cavity and the reflective layer.

Abstract: A method for producing a semiconductor device includes depositing a first oxide insulating film containing an impurity of a first conductivity type on a fourth first-conductivity-type semiconductor layer formed on a substrate; depositing a sixth insulating nitride film; depositing a second oxide insulating film containing an impurity of the first conductivity type; depositing a seventh insulating nitride film; depositing a third oxide insulating film containing an impurity of the first conductivity type; etching the first insulating film, the sixth insulating film, the second insulating film, and the seventh insulating film to form a contact hole; forming a first pillar-shaped silicon layer in the contact hole by epitaxial growth; removing the sixth insulating film and the seventh insulating film; forming a first gate and a second gate; and forming a contact connecting the first gate and the second gate.

Abstract: Phononic metamaterials and methods for reducing the group velocities and the thermal conductivity in at least partially crystalline base material are provided, such as for thermoelectric energy conversion. In one implementation, a method for reducing thermal conductivity through an at least partially crystalline base material is provided. In another implementation, a phononic metamaterial structure is provided. The phononic metamaterial structure in this implementation includes: an at least partially crystalline base material configured to allow a plurality of phonons to move to provide thermal conduction through the base material; and at least one material coupled (e.g., as an inclusion, extending substructure, outer matrix, a coating to heavy inner inclusion, etc.) to the at least partially crystalline base material via at least one relatively compliant or soft material (e.g., graphite, rubber or polymer).

Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, and a buried region. A channel junction is formed between the body region and the high voltage well. The buried region is formed in the substrate and the epitaxial layer, and in a vertical direction, a part of the buried region is located in the substrate and another part of the buried region is located in the epitaxial layer. In the channel direction, an inner side boundary of the buried region is between the drain and the channel junction. An impurity concentration of a second conductive type of the buried region is sufficient to prevent the high voltage well between the channel junction and the drain from being completely depleted when the high-side power device operates in a conductive operation. A corresponding manufacturing method is also disclosed.

Abstract: A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.

Abstract: A liquid crystal display panel and its driving circuit, manufacturing method are disclosed. The driving circuit has a first switching element. The first terminal of the first switching element is connected to one data line of the liquid crystal display panel. At the array manufacturing process stage, the control terminal of the first switching element is input a first reference voltage. The second terminal of the first switching element is connected to a first discharge circuit. During the stage to drive the liquid crystal display panel to display or to test the liquid crystal display panel, the control terminal of the first switching element is input a first control signal. The second terminal of the first switching element is input a data signal. By the aforementioned ways, it can simultaneously achieve an ESD protection and to save the panel space to be favorable for narrow frame design.

Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.

Abstract: A semiconductor structure and a method for fabricating a semiconductor structure are provided. The method includes forming one or more fins on a substrate, wherein each fin includes a first sidewall and a second sidewall opposing each other. The method also includes forming a sacrificial layer over the fin. Further, the method also includes performing a first ion implantation process on the first sidewall and a top of the fin, and performing a second ion implantation process on the second sidewall and the top of the fin.

Abstract: The application discloses an organic light-emitting diode for a display panel. The organic light-emitting diode includes an anode, a cathode, at least two emitting layers arranged between the anode and the cathode, and a charge generation layer arranged between every two adjacent emitting layers, wherein the charge generation layer includes a first layer unit and a second layer unit which are arranged in sequence, the first layer unit includes a hole injection material and a P-type semiconductor material doped in the hole injection material, and the second layer unit includes an electron transport material and ytterbium doped in the electron transport material, wherein a volume concentration of ytterbium doped in the electron transport material ranges from 1% to 5%.

Abstract: An electronics package includes an insulating substrate, a first electrical component coupled to a top surface of the insulating substrate, and a second electrical component coupled to a bottom surface of the insulating substrate. A first conductor layer is formed on the bottom surface of the insulating substrate and extends through a via formed therethrough to contact a contact pad of the first electrical component, with a portion of the first conductor layer positioned between the insulating substrate and the second electrical component. A second conductor layer is formed on the top surface of the insulating substrate and extends through another via formed therethrough to electrically couple with the first conductor layer and to contact a contact pad of the second electrical component.

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a semiconductor fin; a gate dielectric positioned above a first region of the semiconductor fin; a spacer positioned above a second region of the semiconductor fin and adjacent to the gate dielectric; and a source/drain region contacting a third region of the semiconductor fin; wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls.

Abstract: Disclosed are an array substrate and a display device, which can achieve protection of a signal line against static electricity and meanwhile decrease a load on the signal line, so as to improve product yield. The array substrate includes a first signal line, a second signal line and an electrostatic protection device; wherein the electrostatic protection device includes a suspension Thin Film Transistor (TFT), a source electrode of the suspension TFT is connected with the first signal line, a gate electrode of the suspension TFT is connected with the second signal line, and a drain electrode of the suspension TFT is suspended; and wherein the drain electrode and the gate electrode have an overlapping region. The display device includes the above-mentioned array substrate.

Abstract: A manufacturing method of a semiconductor device includes preparing a wiring substrate including a first surface, a plurality of first terminals formed on the first surface, and a second surface opposite to the first surface, arranging a first adhesive on the first surface of the wiring substrate, and after the arranging of the first adhesive, mounting a first semiconductor chip, which includes a first front surface, a plurality of first front electrodes formed on the first front surface, a first rear surface opposite to the first front surface, a plurality of first rear electrodes formed on the first rear surface, and a plurality of through electrodes electrically connecting the plurality of first front electrodes to the plurality of first rear electrodes, on the first surface of the wiring substrate via the first adhesive.

Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

Abstract: A method for fabricating a Fin-FET device includes forming a fin structure on a semiconductor substrate having two peripheral regions and a core region, forming a plurality of dummy gate structures across the fin structure in the core region with each including a dummy gate electrode layer on top and sidewall surfaces of the fin structure, and forming a barrier structure across the fin structure in each peripheral region. The method also includes forming a plurality of source/drain regions in the fin structure between neighboring barrier structure and dummy gate structure and also between neighboring dummy gate structures, and forming a first interlayer dielectric layer at least on the fin structure to cover sidewall surfaces of the dummy gate structures and the barrier structures. Further, the method includes removing the dummy gate electrode layers to form a plurality of openings and forming a metal gate electrode layer in each opening.

Abstract: Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. The semiconductor structures may be used as capacitors, for example, in memory devices. Various methods may be used to form such semiconductor structures and capacitors including such semiconductor structures. Memory devices including such capacitors are also disclosed.