Abstract: A photon detector including a graphene-insulating-superconducting junction configured as a temperature sensor. Photons are absorbed by the graphene sheet of the graphene-insulating-superconducting junction, each absorbed photon causing a temporary increase in the temperature of the graphene sheet, and a corresponding change in the differential impedance of the graphene-insulating-superconducting junction. The graphene-insulating-superconducting junction is part of a resonant circuit connected as a shunt load between a radio frequency input transmission line and a radio frequency output transmission line. The transmission S-parameter from input to output is affected by the impedance of the resonant circuit which in turn is affected by the differential impedance of the graphene-insulating-superconducting junction, and therefore by the temperature of the graphene sheet.

Abstract: This display device is provided with: a circuit substrate having a display region and a non-display region; pixel-driving TFTs for driving pixels, formed in the display region and having source electrodes and drain electrodes being spaced apart from each other on an insulating film and a first active layer formed from an oxide semiconductor, provided on the opposite side from the insulating film so as to cover a separation section between a source electrode and a drain electrode and part of the source electrode and part of the drain electrode adjacent to the separation section; and a driver circuit TFT for driving the pixel-driving TFTs, formed in the non-display region and having a second active layer formed from a non-oxide semiconductor.

Abstract: A system and method for creating layout for non-planar cells with redundancy in one or more of output contacts and power contacts are described. In various implementations, cell layout is created for a first cell with non-planar devices. An available local path in the first cell is identified for redundant output signal routing, which includes a free available metal zero layer track. Redundant metal zero layer is placed in an available metal zero track of the available local path. Redundant contacts and redundant metal one layer are placed in a free track in the available local path to connect an original output contact to a redundant output contact. An available external path is identified between the first cell and a second cell for redundant power or ground routing. One or more metal zero extension layers and/or metal one extension layers are placed in the identified external path.

Abstract: An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin.

Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.

Abstract: A display panel including a display region and a non-display region, a plurality of gate lines, a plurality of data lines, a pixel array and a gate on array circuit. The non-display region is located at one side of the display region. The plurality of gate lines and the plurality of data lines are disposed in the display region. The pixel array is located in the display region, wherein the pixel array is composed of a plurality of pixel units that are repeatedly arranged. The pixel units consist of three gate lines, two data lines and six sub-pixels, and each sub-pixel is electrically connected to one of the gate lines and one of the data lines located in the pixel array respectively. The gate on array circuit is disposed in the pixel array.

Abstract: A semiconductor device has a semiconductor die with a first encapsulant disposed over the semiconductor die. A first build-up interconnect structure is formed over the semiconductor die and first encapsulant. The first build-up interconnect structure has a first conductive layer. The first conductive layer includes a plurality of first conductive traces. A second encapsulant is disposed over the semiconductor die and the first build-up interconnect structure. A second build-up interconnect structure is formed over the first build-up interconnect structure and the second encapsulant. The second build-up interconnect structure has a second conductive layer. The second conductive layer includes a plurality of second conductive traces. A distance between the second conductive traces is greater than a distance between the first conductive traces. A passive device is disposed within the first encapsulant and/or the second encapsulant.

Abstract: A method of forming an active device having self-aligned source/drain contacts and gate contacts, including, forming an active area on a substrate, where the active area includes a device channel; forming two or more gate structures on the device channel; forming a plurality of source/drains on the active area adjacent to the two or more gate structures and device channel; forming a protective layer on the surfaces of the two or more gate structures, plurality of source/drains, and active layer; forming an interlayer dielectric layer on the protective layer; removing a portion of the interlayer dielectric and protective layer to form openings, where each opening exposes a portion of one of the plurality of source/drains; forming a source/drain contact liner in at least one of the plurality of openings; and forming a source/drain contact fill on the source/drain contact liner.

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film on a substrate, the interlayer insulating film including an opening, a barrier conductive film extending along a sidewall of the opening and a bottom surface exposed by the opening, a first film disposed on the barrier conductive film and in the opening, and the first film including cobalt, and a conductive liner on the barrier conductive film, the conductive liner extending along a portion of a side all of the opening and including a metal other than cobalt.

Abstract: A semiconductor device includes a substrate, a plurality of lower electrodes disposed on the substrate and are repeatedly arranged in a first direction and in a second direction that crosses the first direction, and a first electrode support contacting a sidewall of at least one of the lower electrodes. The first electrode support includes a first support region including a first opening and a second support region disposed at a border of the first support region. An outer sidewall of the first electrode support includes a first sidewall extending in the first direction, a second sidewall extending in the second direction, and a connecting sidewall connecting the first and second sidewalls. The second support region includes the connecting sidewall. In a first portion of the second support region, a width of the first portion of the second support region decreases in a direction away from the first support region.

Abstract: A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.

Abstract: Embodiments of the invention include a light emitting diode (LED) including a semiconductor structure. The semiconductor structure includes an active layer disposed between an n-type region and a p-type region. The active layer emits UV radiation. The LED is disposed on the mount. The mount is disposed on a conductive slug. A support surrounds the conductive slug. The support includes electrically conductive contact pads disposed on a bottom surface, and a thermally conductive pad disposed beneath the conductive slug, wherein the thermally conductive pad is not electrically connected to the LED.

Abstract: A semiconductor light-emitting device includes a light-emitting member that includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light-emitting layer between the first semiconductor layer and the second semiconductor layer, a first metal layer electrically connected to the first semiconductor layer, and a second metal layer electrically connected to the second semiconductor layer. The light-emitting member has a first surface including a front surface of the first semiconductor layer, a second surface including a front surface of the second semiconductor layer, a side surface including an outer periphery of the first semiconductor layer, and a recess extending inwardly of the second surface to an interior portion of the first semiconductor layer to expose an inner surface on a side of the recess facing the side surface.

Abstract: A method for fabricating a semiconductor device having a uniform spacer thickness between field-effect transistors (FETs) associated with regions of the device is provided. A first semiconductor material is epitaxially grown in a first source/drain region within a first region of the device associated with a first FET. A capping layer is selectively formed on the first semiconductor material by forming a layer over the first and second regions that reacts with the first semiconductor material to form the capping layer. A second semiconductor material is epitaxially grown in a second source/drain region within a second region of the device associated with a second FET. The capping layer caps the growth of the first semiconductor material during the epitaxial growth of the second semiconductor material to provide the uniform spacer thickness between the first and second FETs.

Abstract: In an embodiment, a method includes forming an intentionally doped superlattice laminate on a support substrate, forming a Group III nitride-based device having a heterojunction on the superlattice laminate layer, and forming a charge blocking layer between the heterojunction and the superlattice laminate.

Abstract: An object of the present invention is to decrease substantial resistance of an electrode such as a transparent electrode or a wiring, and furthermore, to provide a display device for which is possible to apply same voltage to light-emitting elements. In the invention, a auxiliary wiring that is formed in one layer in which a conductive film of a semiconductor element such as an electrode, wiring, a signal line, a scanning line, or a power supply line is connected to an electrode typified by a second electrode, and a wiring. It is preferable that the auxiliary wiring is formed into a conductive film to include low resistive material, especially, formed to include lower resistive material than the resistance of an electrode and a wiring that is required to reduce the resistance.

Abstract: Semiconductor structures including copper interconnect structures and methods include selective surface modification of copper by providing a CuxTiyNz alloy in the surface. The methods generally include forming a titanium nitride layer on an exposed copper surface followed by annealing to form the CuxTiyNz, alloy in the exposed copper surface. Subsequently, the titanium layer is removed by a selective wet etching.

Abstract: A light-emitting element provides a substrate; a plurality of light-emitting cells arranged on the substrate and spaced apart from each other; a connection wire configured to electrically interconnect the light-emitting cells; a first bonding pad electrically connected to the second conductive semiconductor layer of a first light-emitting cell among the light-emitting cells; and a second bonding pad electrically connected to the first conductive semiconductor layer of a second light-emitting cell among the light-emitting cells, wherein a boundary area includes a first boundary disposed between the light-emitting cells adjacent to each other in a first direction among the plurality of light-emitting, and wherein all of the first boundary areas are spaced apart from each other in the first direction.

Abstract: A semiconductor junction may include a first semiconductor material and a second material. The first and the second semiconductor materials are extrinsically undoped. At least a portion of a valence band of the second material has a higher energy level than at least a portion of the conduction band of the first semiconductor material (type-III band alignment). A flow of a majority of free carriers across the semiconductor junction is diffusive. A region of generation and/or recombination of a plurality of free carriers is confined to a two-dimensional surface of the second material, and at the interface of the first semiconductor material and the second material.

Abstract: In an embodiment, an interconnection structure includes a first semiconductor device including a conductive stud, a second device including a contact pad, an adhesive layer including an organic component arranged between a distal end of the conductive stud and the contact pad, the adhesive layer coupling the conductive stud to the contact pad, and a conductive layer extending from the conductive stud to the contact pad. The conductive layer has a melting point of at least 600° C.