Abstract: A light receiving device includes: a photoelectric conversion layer that includes a first compound semiconductor, and absorbs a wavelength in an infrared region to generate electrical charges; a plurality of contact layers that include a second compound semiconductor, and are provided on the photoelectric conversion layer at spacing intervals with respect to one another; and a covering layer that is formed to cover a portion corresponding to the spacing intervals of a front surface of the photoelectric conversion layer and side surfaces of the respective contact layers, and includes a Group IV semiconductor.

Abstract: A compound semiconductor device includes an electron transit layer, a spacer layer disposed on the electron transit layer, and an electron supply layer disposed on the spacer layer and containing a donor impurity. The electron supply layer has a concentration distribution of the donor impurity where the donor impurity is at a first concentration at an interface between the electron supply layer and the spacer layer and at a second concentration lower than the first concentration at an upper surface of the electron supply layer, and a concentration of the donor impurity at one of arbitrarily-selected two positions closer to the upper surface in a thickness direction of the electron supply layer is less than the concentration of the donor impurity at another one of the two positions closer to the interface in the thickness direction.

Abstract: A ferromagnetic multilayer film includes first and second magnetization fixed layers, first and second interposed layers, and a magnetic coupling layer. The magnetization fixed layers are antiferromagnetically coupled by exchange coupling via the interposed layers and the magnetic coupling layer. A main element of the magnetic coupling layer is Ru, Rh, or Ir. A main element of the first interposed layer is the same as that of the magnetic coupling layer. A main element of the second interposed layer is different from that of the magnetic coupling layer. A thickness of the first interposed layer is greater than or equal to 1.5 times and less than or equal to 3.2 times an atomic radius of the main element of the first interposed layer. A thickness of the second interposed layer is less than or equal to 1.5 times an atomic radius of the main element of the second interposed layer.

Abstract: A semiconductor device includes a substrate, a plurality of lower electrodes disposed on the substrate and are repeatedly arranged in a first direction and in a second direction that crosses the first direction, and a first electrode support contacting a sidewall of at least one of the lower electrodes. The first electrode support includes a first support region including a first opening and a second support region disposed at a border of the first support region. An outer sidewall of the first electrode support includes a first sidewall extending in the first direction, a second sidewall extending in the second direction, and a connecting sidewall connecting the first and second sidewalls. The second support region includes the connecting sidewall. In a first portion of the second support region, a width of the first portion of the second support region decreases in a direction away from the first support region.

Abstract: Devices that have integrated cooling structures for two-phase cooling and methods of assembly thereof are provided. In one example, a chip manifold can be affixed to a chip. An interface can be located at a first position between the chip manifold and the manifold cap. Furthermore, the interface can create a seal.

Abstract: This nonvolatile semiconductor memory device comprises: a memory cell array including memory cells; and a wiring line portion connecting the memory cell array to an external circuit. The memory cell array comprises a plurality of first conductive layers which are connected to the memory cells and arranged in a stacking direction. On the other hand, the wiring line portion comprises: a plurality of second conductive layers arranged in the stacking direction and respectively connected to the plurality of first conductive layers, positions of ends of the plurality of second conductive layers being different in a first direction crossing the stacking direction; a third conductive layer extending in the stacking direction from the second conductive layer; a channel semiconductor layer connected to one end of the third conductive layer; and a gate electrode wiring line disposed on a surface of the channel semiconductor layer via a gate insulating film.

Abstract: An integrated DC-DC converter device includes a plurality of GaN transistor sets. A first set of the plurality of GaN transistor sets includes transistors with a first drain-to-source distance, and wherein a second of the plurality of GaN transistor sets includes transistors with a second drain-to-source distance that is greater than the first drain-to-source distance.

Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in an first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.

Abstract: A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.

Abstract: A semiconductor device includes a passivation layer over a dielectric layer, a via through the passivation layer and the dielectric layer, an interconnection metallization arranged over said at least one via; said passivation layer underlying peripheral portions of said interconnection metallization, and an outer surface coating that coats said interconnection metallization. The coating preferably includes at least one of a nickel or nickel alloy layer and a noble metal layer. The passivation layer is separated from the peripheral portion of the interconnection metallization by a diffusion barrier layer, preferably a titanium or a titanium alloy barrier. The device includes a dielectric layer arranged between the passivation layer and the diffusion barrier layer; and a hollow recess area between the passivation layer and the end portion of the barrier layer and between the passivation layer and the foot of the outer surface coating.

Abstract: A magnetoresistance effect element is provided in which a MR ratio is not likely to decrease even at a high bias voltage. A magnetoresistance effect element according to an aspect of the present invention includes: a first ferromagnetic metal layer; a second ferromagnetic metal layer; a tunnel barrier layer that is provided between the first ferromagnetic metal layer and the second ferromagnetic metal layer, in which the tunnel barrier layer is formed of a non-magnetic oxide having a cubic crystal structure represented by a compositional formula A1-xA?xO (A represents a divalent cation, and A? represents a trivalent cation), a space group of the crystal structure is any one selected from the group consisting of Pm3m, I-43m, and Pm-3m, and the number of A ions is more than the number of A? ions in a primitive lattice of the crystal structure.

Abstract: In some embodiments, a first plurality of electron-microscope images for respective instances of a semiconductor structure is obtained from a first source. The electron-microscope images of the first plurality show different values of one or more semiconductor-fabrication parameters. A model is trained that specifies a relationship between the first plurality of electron-microscope images and the values of the one or more semiconductor-fabrication parameters. A second plurality of electron-microscope images for respective instances of the semiconductor structure on one or more semiconductor wafers is collected. The one or more semiconductor wafers are distinct from the first source. Values of the one or more semiconductor-fabrication parameters for the second plurality of electron-microscope images are predicted using the model.

Abstract: The present disclosure can provide a display device, including a substrate, semiconductor light emitting devices having a first conductive electrode disposed on the substrate and formed in a ring shape on an upper edge thereof and a second conductive electrode formed on an upper central portion of the semiconductor light emitting device and surrounded by the first conductive electrode, a passivation layer formed to cover a side surface of the semiconductor light emitting device, and cover part of an upper surface of the semiconductor light emitting device, a first wiring electrode electrically connected to the first conductive electrode, and a second wiring electrode extended from an edge of the semiconductor light emitting device in a central direction of the semiconductor light emitting device to be electrically connected to the second conductive electrode, wherein part of the second wiring electrode overlaps with part of the first conductive electrode with the passivation layer interposed therebetween.

Abstract: A semiconductor device includes a first and second semiconductor chips, a resistive component, and a semiconductor chip including a first circuit coupled to electrodes on both ends of the resistive component. A sealing body has a first long side, a second side, a third short side, and a fourth short side. In a Y-direction, each of the first and second semiconductor chips is disposed at a position closer to the first side than to the second side, while the semiconductor chip is disposed at a position closer to the second side than to the first side. Also, in the Y-direction, the resistive component, the second semiconductor chips, and the first semiconductor chips are arranged in order of increasing distance from the third side toward the fourth side, while the semiconductor chip is disposed at a position closer to the third side than to the fourth side.

Abstract: An interlayer insulating film is disposed on a LOCOS oxide film covering an n-type drift region of a JFET. A polysilicon resistor having a spiral planar shape is disposed in the interlayer insulating film. A spiral wire in an outermost circumference of the polysilicon resistor is covered by a source electrode wire that extends on the interlayer insulating film. An end of the polysilicon resistor is electrically connected to a drain electrode wire. A ground terminal wire and a voltage division terminal wire are electrically connected to a spiral wire farther on an inner circumference side by one or more wires than the spiral wire. A portion farther on an inner circumference side than the spiral wire is used as a resistive element, and voltage for an input pad of the JFET is thereby divided to be taken out as a potential of the voltage division terminal wire.

Abstract: A semiconductor device includes a passivation layer, an interconnection metallization 37 having a peripheral portion over the passivation layer, and an outer surface coating 37 on the interconnection metallization. A diffusion barrier layer comprises an inner planar portion directly on the surface of the passivation layer and a peripheral portion extending along a plane at a vertical height higher than the surface of the passivation layer, so that the peripheral portion forms with the inner portion a step in the barrier layer. The outer surface coating, has a vertical wall with a foot adjacent to the peripheral portion and positioned at the vertical height over the surface of the passivation layer to form a hollow recess area between the surface of the passivation layer and both of the peripheral portion and the foot of the outer surface coating.

Abstract: Embodiments relate to forming nanoporous contacts on a receiving substrate without using a seed layer on the receiving substrate. The nanoporous contacts can be used to create bonds between electronic components and the receiving substrate. To form the contacts, a photoresist mask is created on the receiving substrate by a photolithographic process. Through a sputtering process, portions of co-alloy on a depositing substrate are transferred to the receiving substrate with the photoresist mask. The photoresist mask is removed from the receiving substrate. The remaining co-alloy portions on the receiving substrate undergo a de-alloying process to form an array of nanoporous contacts.

Abstract: A magnetic memory device includes a first magnetic tunnel junction pattern on a substrate, a second magnetic tunnel junction pattern on the first magnetic tunnel junction pattern, and a conductive line between the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern. The conductive line is configured such that a current flowing through the conductive line flows in parallel to an interface between the conductive line and each of the first and second magnetic tunnel junction patterns.

Abstract: An organic light emitting diode display and a method for manufacturing an organic light emitting diode display are provided. An organic light emitting diode display includes: a substrate; a plurality of organic light emitting elements positioned on the substrate; a first alignment mark positioned between the plurality of organic light emitting elements; and a first organic pattern overlapping the first alignment mark on the substrate and including a same material as an organic material included in the plurality of organic light emitting elements.

Abstract: A display device, includes: a display area including an upper side, a lower side, a left side, a right side, and inclined corner portions where the upper, lower, left, and right sides meet; a demultiplexing circuit unit adjacent to the lower side of the display area and the corner portion connected thereto; and a scan transmission line which extends toward the display area from an outer side of the left side and overlaps with the demultiplexing circuit unit outside the corner portion, wherein the demultiplexing circuit unit includes a demultiplexer transistor, and the scan transmission line is formed of a different conductive layer from an electrode of a demultiplexer transistor.