Abstract: A temperature stabilizing circuit for a microwave oscillator employing a field effect transistor on an AsGa substrate, in which a temperature-stabilized frequency is obtained by varying the gate-channel capacitance of an FET included in the oscillator resonance circuit. The capacitance is controlled by a voltage derived from a voltage divider comprising a series arrangement of several Schottky diodes or FET's. The circuit is suited to assembly as an integrated monolithic circuit comprising FETs on a AsGa substrate, for micro wave frequency applications such as for example, processing 12 GHz satellite television signals.

Abstract: A clock pulse generator system for providing a highly stable clock signal consists of two separate redundant clock signal generators which are controlled to operate in dead synchronization with each other. A microprocessor controlled digital phase lock loop operates to control each of the two clock signal generators and selects among a plurality of operating states such that the average dynamic phase difference in the two clock pulse signals generated is practically zero. Furthermore, the instantaneous dynamic phase difference does not exceed the phase noise of the voltage controlled crystal oscillators of the phase lock loops and, in one embodiment, is normally less than ten pico seconds, each phase lock loop comprising means for performing a fine, as well as coarse, phase comparison among internally or externally generated reference signals, only one of which is the highly stable clock signal output.

Abstract: An evacuated wall-coated sealed alkali atom cell for an atomic frequency standard, including a cell bulb having an inner wall subjected to cleaning by means of a bakeout step and a r.f. scrubbing step under vacuum, whereupon the inner wall is provided with a deuterated paraffin coating. An alkali atom .sup.87 Rb and/or .sup.85 Rb, and/or .sup.133 Cs is sealed in the cell bulb under vacuum.

Abstract: A phase lock loop circuit comprises a variable frequency oscillator having a control input and an output, a divider having an input coupled with the output of the oscillator and an output coupled with the first input of a phase or frequency comparator. The comparator has a second input for a reference frequency (F.sub.REF) and an output coupled with the oscillator control input for providing a signal which is related to the difference in phase or frequency of the signals at the first and second inputs to effect phase locking of the oscillator to the reference signal. A detector provides a switching signal when the control signal falls outside a predetermined range and a switch in the phase lock loop is responsive to the switching signal to open the loop.

Abstract: A voltage controlled oscillator comprises a tank circuit for determining an oscillation frequency, a first circuit for delaying the signal having the oscillation frequency, a second circuit for advancing the signal having the oscillation frequency, the first and second circuit being connected in series, a third circuit interposed between the tank circuit and the series connection of the first and second circuits, the third circuit having the same equivalent circuit of the series connection, a first gain controlled amplifier amplifying the output from the first circuit, a second gain controlled amplifier amplifying the output from the second circuit, an adder for adding outputs from the first and second gain controlled amplifiers, a control circuit controlling the gains of the first and second gain controlled amplifiers, and a feed-back circuit for feeding the output of the adder to the tank circuit.

Abstract: A temperature and voltage stable clock circuit for use in implantable cardiac pacers employs CMOS devices to minimize current drain. The circuit includes a timing capacitor which is alternately charged to and discharged between two established threshold voltages during respective charge and discharge cycles, the periods of which determine the clock frequency. To render the frequency of the clock circuit independent of changes in capacitor charge and discharge currents brought about by changes in temperature, the threshold voltage is increased with temperature so that the charge and discharge cycles remain constant. To render the frequency of the clock circuit independent of changes in the power supply voltage, a Wilson current source is used to maintain a constant charge and discharge current to the timing capacitor.

Abstract: A low power, wide bandwidth oscillator capable of oscillating at frequencies of greater than 350 MHz and capable of being implemented in relatively few parts is disclosed. A switching section controls the resonant frequency of a resonator and is connected in DC series with an amplifier. A regulator-buffer section simultaneously serves as a voltage regulator and RF signal buffer.

Abstract: An oscillation circuit includes as its principal components a Clapp capacitor and two feedback capacitors connected to each other and a resonance coil. A first series circuit including a first variable-capacitance diode and a first DC cutoff capacitor is connected in parallel with the resonance coil, while a second series circuit including a second variable-capacitance diode and a second DC cutoff capacitor is connected to a first diode such that a certain polarity terminal of the second variable-capacitance is faced against the same polarity terminal of the first diode. One end of the second DC cutoff capacitor in the second series circuit is connected to the one of the feedback capacitors. Furthermore, means is provided at the joint of the first variable-capacitance diode and the first DC cutoff capacitor for applying a DC voltage to enable the first and second variable-capacitance diodes.

Abstract: A switching circuit apparatus driven by a relatively low DC power supply voltage, which includes a power supply terminal designed to receive a DC power source voltage, a pair of switching circuits comprising switching transistors (28, 30 and 32, 34) connected in parallel with each other and connected to the power supply terminal, first circuit means (10,12) connected for supplying the respective switching circuits with a switched signal, and a second circuit means (16, 18, 40, 14) connected for supplying the respective switching circuits with a pair of control signals which are opposite in phase and which are never both at a potential difference other than a prescribed potential at the same time. The switching circuit transistors (28, 30 or 32, 34) are all fully conductive prior to any transition in which two are rendered non-conductive by the control signals, thereby enable operation of the circuit with low power consumption.

Abstract: A phase locked loop circuit (16) includes means to eliminate harmonic frequency locking. The phase locked loop includes a voltage controlled oscillator (1) which provides an output signal (V.sub.out) which is compared with the input signal (V.sub.in) by a phase detector (4). The output signal from the phase detector is integrated and the output signal of the integrator (7) is placed on the control input lead of the voltage controlled oscillator. The output signal of the voltage controlled oscillator is provided to a frequency detector (14, 17) which determines if the output frequency is within a predefined range. If the output frequency is above the predetermined range, a limiter circuit (15) provides a low voltage output signal to the control input lead of the VCO in order to pull the input voltage of the VCO to a voltage which corresponds with the appropriate operating range of the phase locked loop.

Abstract: A microwave solid-state oscillator includes a casing hermetically enclosing a microwave oscillation device and a dielectric resonator electromagnetically coupled with the microwave oscillation device, an output terminal leading out an oscillation output from said casing, and a microwave terminal electromagnetically coupled to the dielectric resonator, one end of which is connected to a microwave line having a terminating admittance at the outside of the casing.

Abstract: A low current oscillator/buffer amplifier configuration is disclosed which provides a simple, inexpensive, low power oscillator with reduced harmonic output. Buffer 60 is coupled to the resonant tank circuit 58 of oscillator 50 by means of impedance transform network 70. This technique of tapping directly from the tank provides a buffered output signal having low harmonic content. Furthermore, impedance transform network 70 permits coupling feedback amplifier 52 to buffer amplifier 62 in a totem-pole amplifier stage configuration. This feature provides a significant current savings over conventional oscillator/buffer circuits. The instant invention is particularly well adapted for use as reference frequency oscillators in portable radio applications.

Abstract: An analog phase interpolator for use in Fractional-N frequency synthesis is disclosed. The interpolator employs a precision gating circuit adapted to generate analog signals indicative of a precisely determined time interval. The signals switch a precision correction current to precisely compensate for the phase detector "beat note" to reduce the magnitude of FM spurious signals. The time interval is inversely proportional to the synthesizer output frequency and the gating circuit automatically compensates for changes in the output frequency. The precision gating circuit includes a prescaler circuit for prescaling the output signal frequency to provide a clock signal, and is responsive to an "initiate" pulse to provide two pulses delayed by a predetermined number of clock signal periods. A very high degree of time integrity exists in the relation of the edges of the two pulses.

Abstract: The present invention uses digital values of MSK-like waveshapes which can be stored in a storage media such as a ROM and then output in a prescribed fashion such as in phase quadrature through the use of an addressing technique to the ROM. The digital values, each of N bits, are then multiplied in quadrature times a data representative signal which is divided into phase quadrature components. These N+1 bit products are summed to produce a composite digital signal representing analog bipolar values. A digital-to-analog conversion provides the modulated analog output signal.

Abstract: A phase modulator includes a digital frequency word generator, an adder and a register arranged to generate recurrent digital sawtooth signals at a carrier rate. A second digital adder is coupled to receive the sawtooth signals and also receives digital information signals. The adder produces recurrent digital sawtooth signals phase-modulated by the information signal. A pair of adders receive the digital sawtooth signals and mutually sign-reversed digital information signals to produce a pair of oppositely phase-modulated constant-amplitude signals in a pair of channels. A sine memory is addressed by the phase-modulated digital sawtooth signals to produce phase-modulated sinusoidal-representative digital signals. The digital signals are then converted to analog signals. Since the two channels contain signals which are phase-modulated but not amplitude-modulated, the signals may be amplified by nonlinear amplifiers.

Abstract: An all digital circuit which operates with an electronic oscillator of the type that receives an input signal and synchronizes its oscillations to transitions in the input signal, comprises: a pulse-generating circuit 20 coupled to the oscillator for digitally forming periodic pulses in synchronization with selected oscillations of the oscillator; a detecting circuit 30 coupled to receive the pulses and the input signal for digitally detecting whether a transition occurs in the input signal in the absence of a pulse; and a counting circuit 40 coupled to the detecting circuit for digitally counting so long as the detecting circuit fails to detect a transition in the absence of a pulse and for indicating the oscillator is synchronized when the count reaches a predetermined number.

Abstract: A frequency time standard monitoring system includes three highly accurate standards of substantially identical frequency. These three standards are compared in pairs by three monitoring apparatus. Each such apparatus includes a fine window detector for determining the phase relationship between the two applied frequency standard clock signals, and a phase shifter responsive to the fine window detector for shifting the phase of one of the signals until the signals are phase aligned. When this occurs, the fine window detector is disabled and a coarse window detector monitors the two clock signals to ensure that the clocks do not drift beyond tolerable limits. The output signal of the coarse window detector is applied, along with the corresponding signals from the other two monitoring apparatus, to a select logic which determines which standard should be on-line in the event of a fault detection.

Abstract: The acquisition of phase lock to a reference frequency by a signal acquisition system is accomplished using a voltage controlled oscillator, a wideband frequency discriminator, a prepositioning circuit, and a phase lock loop. The voltage controlled oscillator is prepositioned within a loop bandwidth of the reference frequency by the prepositioning circuit and the wide band frequency discriminator which provide coarse tuning. The voltage controlled oscillator achieves phase lock with the reference frequency when it receives the fine tune signal from the phase lock loop. Using both the discriminator and the phase lock loop allows fast acquisition without the need to calibrate the voltage controlled oscillator. Since the discriminator pull-in range is much larger than the phase-lock loop bandwidth, the number of bits can be much smaller than in an acquisition circuit using a digital prepositioning circuit alone.

Abstract: Apparatus is depicted which enables the sampling of the phase angle of a modulated signal and manipulates the sample signals to demodulate the same. The apparatus is particularly adaptable for use in demodulating the I and Q channel signals of a zero IF receiver. The system contains an angle sensing circuit which combines the I and Q channel signals in differential form to produce a series of output signals of an angular range indicative of the present value of the instanteous phase. The signals from the angle detector are coupled to an octant decoder which operates to determine the particular octant that the angle is to be included in. In the present system eight octants are used, each comprising 45.degree.. The octant decoder determines which octant the angle belongs in and assigns a predetermined angle value to that angle. In one embodiment, the assigned angle values are 0.degree., 45.degree., 90.degree., 135.degree., 180.degree., 225.degree., 270.degree. or 315.degree..

Abstract: An FM signal demodulating circuit which provides accurate drop-out compensation without producing an unnatural sounding output. The period of the receive FM signal is periodically detected for each cycle thereof to produce a signal having a level corresponding to the period of the FM signal. The signal so derived is held for each period of the FM signal, including periods during which drop-out occurs. The reciprocal of the level of the held signal forms the demodulated output signal.