Abstract: A digital sine/cosine wave generator generates discrete values representative of either a sine wave or a cosine wave. The digital sine/cosine wave generator generates sine and/or cosine waves by implementing a difference equation of the form y(n)=b*y(n?2)?y(n?1). One of the initial conditions of the difference equation is selected from a series of values generated by a coefficient generator. The frequency of the sine and/or cosine wave generated by the sine/cosine wave generator is dependent on, and may be selected according to, which of the series of values generated by a coefficient generator is chosen as an initial condition of the difference equation.

Abstract: Various methods for performing rounding operations in a computer processor are described. A machine instruction sets the rounding mode, which is automatically applied to subsequent machine instructions. Using machine instructions to round results according to the selected rounding mode has several advantages over software-implemented rounding techniques, such as faster execution and concise code. A variety of rounding modes can be specified. Depending in part on the specified rounding mode and on the sign of the value to be rounded, a rounding term is added to the value to be rounded. Adding this rounding term ensures that the desired result is obtained. The value thus obtained is then right-shifted.

Abstract: Implementations of a two-dimensional pyramid filter are disclosed including a two-dimensional pyramid filter architecture of an order 2N?1, where N is a positive integer greater than three. The two-dimensional pyramid filter architecture of order 2N?1 may include one-dimensional pyramid filters of order 2N?1, a first summer circuit; and a second summer circuit. The two dimensional pyramid filter architecture of order 2N?1 may produce, in operation on respective clock cycles, at least a pyramid filtered output signal corresponding to the summation by the first summer circuit of output signals produced by four one-dimensional pyramid filters of order 2N?1, and a pyramid filtered output signal corresponding to an output signal produced by summing signal sample matrices of order [2(N?1)?1] in the second summer circuit. The respective pyramid filtered output signals of the two dimensional pyramid filter architecture may be summed by the third summer circuit on respective clock cycles.

Abstract: A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.

Abstract: The present invention relates to a barrel shifter for manipulating bits within computer words. The barrel shifter includes multiple multiplexer stages for rotating single and multiple words. In several embodiments, it provides a half-word alignment in a 2n-bit barrel shifter, rotates a single 32-bit data word or two 16-bit data words, rotates a 2n-bit data word or two 2n?1-bit data half-words, a method of operating a 2n-bit barrel shifter to rotate two 2n?1-bit data words, multiplexer stages for rotating the bits to the left or right based on control signals, such that the stages do not require 2:1 multiplexers between the first and second stages.

Abstract: A random number generator includes a first oscillator that provides a first oscillatory signal to a processor, and a second oscillator that provides a signal to a frequency multiplier, which in turn provides a second oscillatory signal to the processor. The relative jitter between the two oscillatory signals contains a calculable amount of entropy that is extracted by the processor to produce a sequence of true random numbers.

Abstract: A computing device (40) comprises an electrical circuit and a software application. A display screen (138) and an input device (140) are electrically coupled to the electrical circuit. The software application provides instructions to determine the number of significant figures for a number entered via the input device, and simultaneously display on the display screen the entered number along with the number of significant figures for the entered number, and/or the software application provides instructions to calculate a floating point answer for a mathematical operation entered for one or more numbers entered into the computing device, round the floating point answer to the proper precision or to the proper number of significant figures, determine the number of significant figures for the rounded answer, and simultaneously display on the display the rounded answer and its number of significant figures.

Abstract: A method for calculating greatest common divisors uses an approximate division in its reduction step. The result of this approximate division is then compared to determine if it is valid. If not, then the method applies a correction to the first approximate division to determine corrected values that have a reduced number of bits. If, during this correction step, the result is again not valid, then another method is applied to reduce the number of bits in the values. The approximate division is applied only when the number of significant bits in the two values differ by at least a predetermined number. When the number of bits in the two values differ by less than this number, an alternative GCD algorithm is applied but only to reduce the number of bits in the intermediate values.

Abstract: A random number generation system and method use the randomness in hardware circuitry start-up to generate a random seed for a random number. In a preferred embodiment, the instability of a phase locked loop is used.

Abstract: The present invention provides a method for performing a point doubling operation with only one modular division and no multiply per operation. As a result, the invention reduces the number of mathematical operations needed to perform point doubling operations in elliptic curve computation. An elliptic curve cryptosystem using the present invention can be made to operate more efficiently using the present invention. An elliptic curve crypto-accelerator can be implemented using the present invention to dramatically enhance the performance of the elliptic curve cryptosystem. The invention derives the slope of a curve independently of the y-coordinate. By avoiding the calculation of the y term, one additional multiply is eliminated from each point-doubling operation. Using the invention, n consecutive point doublings can be reduced to n modular divisions and 1 multiply. This avoids the 2n multiplies of prior art approaches.

Abstract: The invention concerns a complex number multiplier receiving the binary number A, B, C and D complementarily coded in pairs so as to perform the complex multiplication (A+jB)*(C+jD). A first processing stage enables to perform the operations A−B, C−D, and A+B whereof the results are binary numbers in base two with a redundant binary format, and a borrow-save coding for subtractions and carry-save coding for addition. A second processing stage converts said results into coded binary numbers in base four. A third processing stage enables to perform multiplication (A−B)C, (C−D)B and (A+B)D with a redundant binary format and a borrow-save coding. A last stage comprises two adders for working out the real part (A−B)C+(C−D)B and the imaginary part (A+B)D+(C−D)B in a redundant binary format and a borrow-save coding.

Abstract: The present invention provides an efficient method for bypassing outputs while in redundant form to an arithmetic circuit that is capable of adding or subtracting numbers in redundant from and comparing the magnitudes of numbers received in redundant form for equality and inequality relationships. For one embodiment of the invention, an arithmetic circuit subtracts numbers received in redundant form and compares the result to zero represented in redundant form without carry propagation. In parallel with the subtraction and comparison, the most significant bits of each number received in redundant form are generated and compared for equality, and a carry-out is generated for the subtraction. These results are combined by magnitude comparison logic to produce a magnitude comparison for the numbers received in redundant form.

Abstract: Montgomery exponentiators and methods modulo exponentiate a generator (g) to a power of an exponent (e). The Montgomery exponentiators and methods include a first multiplier that is configured to repeatedly square a residue of the generator, to produce a series of first multiplier output values at a first multiplier output. A second multiplier is configured to multiply selected ones of the series of first multiplier output values that correspond to a bit of the exponent that is binary one, by a partial result, to produce a series of second multiplier output values at a second multiplier output. By providing two multipliers that are serially coupled as described above, Montgomery exponentiation can be accelerated.

Abstract: In accordance with the preferred embodiment of the present invention a gain (A) is determined and utilized to cyclically converge upon a quotient (Q). More particularly, once A is determined, an estimate of QN is multiplied by Y to estimate {circumflex over (X)}N, where Q=X/Y. The value of {circumflex over (X)}N is then subtracted from X to determine an error (eN), which is multiplied by A. The value of AeN(n) is added to AeN(n−1) to produce an estimate of Q. Once convergence has occurred, the value for Q is output from the circuitry.

Abstract: An embodiment of the invention described in the specification and drawings is an apparatus and method of generating a phase-shifted maximum length pseudo-random noise (PN) sequence without resorting to complicated counters and clocking schemes. The apparatus includes a linear feedback shift register (LFSR) that has N stages and the ability to generate a first PN sequence at an output of its last stage. The LFSR is coupled to a first mask circuit and a second mask circuit for generating a second PN sequence and a third PN sequence. The apparatus further includes logic for selectively outputting bits from the second and third PN sequences to form a fourth PN sequence, which has a phase shift relative to the first PN sequence.

Abstract: In a modular arithmetic apparatus including a plurality of product-sum circuits having a modular arithmetic function and parallelly arranged, and a correction term calculation unit for calculating a correction term to be used for modular arithmetic operation in the product-sum circuits, the correction term calculation unit sequentially calculates the correction term in units of bits, and each of the product-sum circuits sequentially reflects the correction term calculated by the correction term calculation unit and performs base conversion or base extension.

Abstract: A digital true random number generator circuit, comprising a linear feedback shift register having an input and an output, a system clock having a system clock frequency value for driving the shift register, and a plurality of free running oscillators operatively connected to the input of the shift register. The oscillators and the system clock having different oscillation frequency values, the greatest common divisor of which having the value one, thereby avoiding locking of the oscillators and the system clock.

Abstract: A method and an apparatus are provided for combining a plurality of random number generators into a combined random number generator. The outputs of the plurality of generators are interleaved into a combined stream of random numbers selected from each of the plurality of random-number generators. A value of x is calculated by each of the random number generators. Each of the values of x is mapped to a respective arrival time t for each of the random number generators. One of the random number generators having an earliest respective arrival time t is determined. A random number based on the arrival time t is generated.