Abstract: A method and system determine a high part of a floating point operand. Exponent field bits and fraction field bits of a result are set to a zero if the determined format is an infinity format or an overflow format. The exponent field bits and the fraction field bits of the result are set to corresponding exponent field bits and corresponding fraction field bits of the floating point operand if the determined format is a not-a-number (NaN) format. At least one of the fraction field bits of the result is adaptively cleared if the determined format is a denormalized format or a delimited format.

Abstract: A microprocessor structure for performing a discrete wavelet transform operation, said discrete wavelet transform operation comprising decomposition of an input signal comprising a vector of r×km input samples, r, k and m being non-zero positive integers, over a specified number of decomposition levels j, where j is an integer in the range 1 to J, starting from a first decomposition level and progressing to a final decomposition level, said microprocessor structure having a number of processing stages, each of said number of processing stages corresponding to a decomposition level j of the discrete wavelet transform operation and being implemented by a number of basic processing elements, the number of basic processing elements implemented in each of said processing stages decreasing by a factor of k from a decomposition level j to a decomposition level j+1.

Abstract: A data interpolating device comprises plural stages of delay circuits (1?1, 2?1, 3?1) for delaying discrete data sequentially inputted and multiplication/addition circuits (4?1 to 16?1) that performs weighted addition of data outputted from the output stages of the plural stages of delay circuits (1?1, 2?1, 3?1) according to the value of a digital basic function (?1, 1, 8, 8, 1, ?1) and thereby determine interpolation data. Since a sampling function of finite supports differentiable once or more times over the whole range.

Abstract: A multiplier (42) forms a product from two signed operands without performing a sign extension of the multiplicand (A). A modified Booth's recoding of the multiplier operand (B) is begun immediately without being delayed by a sign extension operation. While recoding and partial product generation is occurring, a determination is made in parallel whether or not a sign extension adjustment term must be created. When needed, a value equal to (?B) (2N), where N is equal to a bit width of the multiplicand (A), is formed in parallel with the recoding and partial product generation. The sign extension adjustment term is coupled to a plurality of carry save adders (49, 51, 53) that compress a plurality of partial products to a sum term and a carry term. A final add stage combines the sum term and carry term to provide a product with correct sign extension.

Abstract: A floating point flag forcing circuit comprising an circuit and a result assembler. The circuit receives a plurality of floating point operands, analyzes the floating point operand, receives one or more control input signals, determines one or more predetermined formats in which the plurality of operands are represented, and generates one or more control signals. The result assembler receives the control signals from the circuit, along with one or more inputs, and assembles a result.

Abstract: A matrix calculator calculates multiplication of two matrices. The matrix calculator includes an element selecting portion for selecting elements from elements of the two matrices that would constitute sub-elements of each element of a multiplication result matrix and sequentially outputs the selected element, a calculating portion for adding products of output from the element selecting portion and sequentially outputs the elements of the result matrix, and a control signal generating portion for generating a control signal that controls a timing of operation of the calculating portion and the storing portion. Since the respective elements of the two matrices are sequentially selected to be multiplied and added, the elements of the multiplication result matrix, which are the sums of the sub-elements, can be calculated sequentially. Accordingly, since the matrix calculator can be constructed of one adder and one multiplier and a control circuit, the size of the circuit is reduced.

Abstract: Systems and methods to implement an improved floating point adder are presented. The adder integrates adding and rounding. According to an exemplary method, of adding two floating point numbers together, a first mantissa, a second mantissa, and an input bit are added together to produce a third mantissa. The third mantissa is normalized to produce a final mantissa. The third mantissa and the final mantissa are correctly rounded as a result of the act of adding, so that the final mantissa does not require processing by a follow on rounding stage.

Abstract: A pipelined processor such as an averaging filter including at least one subtractor section and at least one adder section. Both of the subtractor section and the adder section have a plurality of adder logic units. In comparison to the conventional processor, the processor of the present invention is streamlined by the application of one or more of three techniques. First, there is the interleaving approach where the subtractor section and the adder section are interleaved with one another. Second, there is the one delay feedback approach where the adder section includes a one delay feedback for each of the adder logic units. Third, there is the delay enable signal output approach where the averaging filter includes a delay enable signal output for each of the adder logic units of the adder section.

Abstract: A self-timed data processing circuit module is provided. Data is provided to the data processing circuit along with a Req handshaking input. The data processing circuit has an isochronous processing delay for all data inputs. An example of a data processing circuit with isochronous processing delay is a One Hot Residue Number System arithmetic processing circuit. The data processing circuit processes the input data while the Req input propagates through a delay circuit that has substantially the same processing delay as the data processing circuit. Thus, the propagation delay of the Req signal is substantially equal to the data processing circuit's processing time. This allows the output of the delay circuit to be used to both latch the output of the data processing circuit and provide a “data ready” output.

Abstract: In one embodiment of the present invention, a high-speed adder is provided. This adder may incorporate a conversion circuit in a slack propagation timing path to provide for improved performance. The present invention may be incorporated into single or multi-bit adders.

Abstract: An improved adaptive line enhancer includes an adaptive Gray-Markel lattice notch filter having an adaptive notch frequency, in which the notch frequency is determined according to a notch frequency variable k. The value of k for the n+1th sample period is determined according to the following equation: k(n+1)=k(n)?sgn[y(n)]sgn[UPDATEFN]×? in which y(n) is the notch filter output, ? is the adaptation constant, and UPDATEFN has a transfer function in the z-transform domain of: ( ? - 1 ) ? ( k ? ( n ) - 1 ) ? z - 1 1 + k ? ( n ) ? ( 1 + ? ) ? z - 1 + ? ? ? ? z - 2 in which ? determines the bandwidth and k(n) is a variable for determining the current notch frequency. The algorithm for adapting the notch frequency enables the notch frequency to be directly calculated from knowledge of internal variables of the wave digital filter.

Abstract: A method and processor for multiplying two maximally negative fractional numbers to produce a 32-bit result are provided. Operands are fetched from a source location for operation of a multiplication operation. Result outputs corresponding to a maximally negative result are detected. The detection of a maximally negative result indicates that the operands are two maximally negative fractional numbers. Maximally negative results are corrected to produce a maximally positive result. Result output are fractionally aligned and sign extended for accumulation in an accumulator.

Abstract: Three-dimensional data that is processed is divided by the number of threads in the third dimensional direction and stored to respective secondary cache memories of the threads. Each thread Fourier transforms data stored in the secondary cache in the first dimensional direction and the second dimensional direction. As a result, a two-dimensional Fourier transform can be performed in parallel at a time. The resultant data that has been two-dimensionally transformed is restored to a shared memory. Each thread Fourier transforms the data in the third dimensional direction.

Abstract: The subject invention provides a system and method for quick and easy calculation of medication dosages to overcome problems in current methods and systems for calculating dosages. The invention can be implemented in numerous ways, including as a system, a device, a method, or a computer readable medium. Specifically exemplified herein are embodiments for use in the healthcare industry.

Abstract: A method for fast median filtering in an implantable medical device is disclosed that provides rapid filtering using computational mechanisms with following elements. A new sample value is received into a buffer. An oldest sample value location is identified in a MIN-heap and a MAX-heap. A new sample value location is identified in either the MIN-heap or the MAX-heap by comparing the new sample value to a median value. The new sample value is placed into the oldest sample value location, if the MIN-heap or MAX-heap identified for the new sample value location is the same as the MIN-heap or MAX-heap identified for the oldest sample value location. A MIN-heap top or MAX-heap top is moved from the heap not containing the oldest value into the location of the oldest sample and the new sample is placed into the location of the MIN-heap top or MAX-heap top moved from the heap not containing the oldest value, if the heap identified for the new sample is not the same as the heap identified for the oldest sample.

Abstract: A handheld computing device (40) comprises a software application adapted to provide instructions to graphically display a vector on a display screen (48) simultaneously along with the numerical values for components of the vector. The software application may be further adapted to provide instructions to perform a vector math operation on one or more vectors, to allow a user to pick the vector for use in the vector math operation, concurrently while graphically viewing the vector on the display screen (48) simultaneously with its numerical values for components, and/or to allow a user to graphically input the vector by incrementing a vector component with an arrow key (101-104) on the input device (50), concurrently while graphically viewing the vector and vector changes on the display screen (48).

Abstract: A method of calculating the fast Fourier transform or the inverse fast Fourier transform of a series of N real samples x(n), with N power of two, operating according to a time interleaving algorithm and providing the sample series X(n) in ascending order to index n and using limited calculating storage means. A method of calculating the fast Fourier transform or the inverse fast Fourier transform of a series of N conjugated complex samples X(n), with N power of two, operating according to a frequency interleaving algorithm.

Abstract: A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinatins of each bit of a binary number with each other bit of another binary number is generated having a reduced from in order to reduce the steps required in array reduction.

Abstract: A method and an apparatus for performing a shift operation on an operand. The method and apparatus configures input lines to comprise a first part that includes the bits in order representing various shift amounts in a first direction and a second part that includes bits ordered representing various shift amounts in a second direction. The shift is then performed by selecting the appropriate bits from the input line to create the result.

Abstract: An adder based circuit embodied in an integrated circuit includes an input module, a carry module and an output module. The carry module has a minimum depth defined by a recursive expansion of at least one function associated with the carry module based on a variable k derived from a Fibonacci series. Invertor, XOR, XNOR (more preferably, OR(NOT(a),b)) and multiplexer elements are selectively coupled to the input and output modules to configure the adder based circuit as a subtractor, adder-subtractor, incrementor, decrementor, incrementer-decrementor or absolute value calculator. A computer process of designing the adder base circuit recursively expands the functions, and optimization of death, fanout and distribution of negations is performed.