Abstract: A zero-knowledge proving system includes a proving mechanism for proving equality or inequality of two discrete logarithms and a verifying mechanism for verifying said equality or inequality. The proving mechanism stores public information including a designated operation scheme, two input numbers ? and ?, and two predetermined bases g and h, private information x which is a discrete logarithm of ? to the base g. After converting ?, ? and h to produce ??, ?? and ?? as follows: ??=?r; ??=?r; and ??=hxr, the equality of a log??? and log??? and the equality of logg?? and logh?? are proved. The verifying mechanism verifies the equality of a log??? and log??? and the equality of logg?? and logh??. Then, the received ?? and ?? are checked to determine the equality or inequality thereof, and it is determined whether the proof is acceptable, depending on the verification and the check results.

Abstract: A method and apparatus for performing a radix-4 fast Hadamard transform (FHT) with reduced complexity and for directly determining the maximum output of a fast Hadamard transform using either a radix-4 transform or radix-2 transform without actually generating the outputs. The radix-4 fast Hadamard transform is implemented using only seven operations. To find the maximum value of the output of a fast Hadamard transform and its corresponding index, the N?1 stages of a conventional N stage fast Hadamard transform are computed while a find-maximum stage is inserted in place of the Nth stage. The invention also provides a methodology for constructing fast Hadamard transforms of the form H2N using radix-4 FHTs and permuting the results to achieve the correct outputs.

Abstract: The indication of a status affected by the performance of an ALU mathematical operation is provided. The indication includes the setting and clearing of a status bit in a status register based on the production of an arithmetic result of zero by an ALU performing the ALU mathematical operation. The result may comprise a series of results, each result produced by an ALU mathematical operation instruction executed to perform the ALU mathematical operation. Indicating a status affected by the performance of the ALU mathematical operation instruction further includes determining whether the ALU mathematical operation instruction corresponds to an ALU mathematical operation instruction with carry as well as determining whether the result is a non-zero value. The status bit maintains a value of zero upon the production of a non-zero value until an ALU mathematical operation instruction without carry is determined.

Abstract: A random number generation system, including a turbulent fluid source, a pressure sensor adapted to monitor a pressure of the turbulent fluid source, and a computation module operatively connected to the pressure sensor the module adapted to generate a numeric representation of the pressure.

Abstract: A calculation circuit for the division of a fixed-point input signal comprising a sequence of digital data values having a width of n bits by an adjustable division factor 2a for the purpose of generating a divided fixed-point output signal, having a signal input (2) for applying the data value sequence of the fixed-point input signal, a first addition circuit (6), which adds the digital data value present at the signal input (2) to a data value buffer-stored in a register (33) to form a digital first summation data value having a width of max (n, a+1)+1 bits, a shift circuit (11) which shifts the first summation data value present by a data bits toward the right, with the result that the max (n, a+1)?a+1 more significant data bits of the first summation data value are output at an output of the shift circuit (11), a logic circuit (16), which, as a function of the sign of the first summation data value, logically ANDs the a less significant data bits of the first summation data value with a logic combination

Abstract: A method and apparatus for performing a radix-4 fast Hadamard transform (FHT) with reduced complexity and for directly determining the maximum output of a fast Hadamard transform using either a radix-4 transform or radix-2 transform without actually generating the outputs. The radix-4 fast Hadamard transform is implemented using only seven operations. To find the maximum value of the output of a fast Hadamard transform and its corresponding index, the N-1 stages of a conventional N stage fast Hadamard transform are computed while a find-maximum stage is inserted in place of the Nth stage. The invention also provides a methodology for constructing fast Hadamard transforms of the form H2N using radix-4 FHTs and permuting the results to achieve the correct outputs.

Abstract: A digital filter having the capability to completely prevent the digital filter from generating the overflow oscillation by detecting positive and negative overflow propagating one or a plurality of bits by means of an overflow detecting circuit. When overflow is detected, a clipping circuit serves to fix the output signal to a positive maximum value or a negative maximum value.

Abstract: An extended exponent floating point unit performs an extended exponent floating point operation on a plurality of operands to produce a product of the plurality of operands. The extended exponent floating point unit groups the plurality of operands into at least one group, determines a plurality of scale factors for the plurality of operands, respectively, and provides a running sum of the plurality of scale factors. The extended exponent floating point unit further scales the plurality of operands to obtain a plurality of scaled operands, multiplies the plurality of scaled operands to obtain a group product, and scales the group product to obtain a scaled group product. The scaled group product is adjusted based on the running sum. The plurality of operands are grouped such that when all the plurality of scaled operands in the at least one group are multiplied an overflow or underflow will not occur.

Abstract: An address generator for use in conjunction with a fast Fourier transform processor includes an efficient architecture for computing the memory addresses of input data points, output data points and twiddle coefficients. In particular, multiplication operation in the calculation of memory addresses is minimized. Instead, a cascaded series of adders is used, in which the output of one adder is input to the next adder. At each stage of the cascaded adders, the same input variable is successively added. The cascaded adder structure is used in the writing address generator, the reading address generator and the twiddle coefficient address generator. In addition, a plurality of modulo N circuits is used in series with the cascaded series of adders to generate the twiddle coefficient addresses.

Abstract: An integer transform matrix is used for implementing a Discrete Cosine Transform (DCT). Optimized values for the integer transform matrix are derived that satisfy certain normalization constraints and that also minimize the frequency distortion in the transform matrix.

Abstract: A squaring multiplier for a floating-point number comprises: a pseudo carry generator for generating pseudo information concerning a carry equivalent to predetermined bits for the calculation of a target variable; an MSB look ahead circuit for employing the variable to perform a look ahead operation and establish the location of the MSB (Most Significant Bit) in the calculation results; and combinational circuits for performing the rounding off process and the calculation of the variables by using information concerning a carry, which is generated by the pseudo carry generator and based on the location of the MSB determined by the MSB look ahead circuit.

Abstract: A process for converting signals in the form of digital data, such as various types of video/audio/data signals for example, between an original format, in which each data item includes a certain number of digits, and a compressed format, in which each data item includes a smaller number of digits. The process includes the operation of associating the data with a configuration including: a first field identifying the number of sub-blocks into which the said certain number of digits are subdivided, a second field that identifies, within the said sub-blocks, respective sections, each one including a given number of digits, and a third field that identifies, for each these sections, one of a plurality of applicable modes (average, compression, transmission “as is”, etc.) that can be adopted for converting the digits in the section between the original format and the compressed format.

Abstract: A leading one correction circuit receives a significand from a floating point adder and a corresponding leading one prediction from a leading one predictor, and determines if the leading one prediction is correct. In one embodiment, the leading one prediction is a one hot vector having the same number of bits as the significand, with the set bit in the position predicted to have the leading one. In such an embodiment, the leading one correction circuit may perform a bitwise AND of the significand and leading one prediction, and the result of the bitwise AND may be ORed to generate a signal indicating whether or not the prediction is correct. In one implementation, the leading one correction circuit may operate concurrent with a shift of the significand in response to a shift amount indicated by the leading one prediction.

Abstract: An arithmetic unit for adding a plurality of values to define a result, the arithmetic unit including circuitry for receiving the plurality of values; circuitry for adding the plurality of values to define a result, the result being within a first range; circuitry for determining if the result falls within a second range, the second range being smaller than the first range, the circuitry arranged to consider only some of the bits of the result; and circuitry for modifying the result in so that the result output by said arithmetic unit falls within the second range.

Abstract: A low power tap multiplier multiplies a m-bit multiplier and a n-bit multiplicand to output a p-bit multiplication product. The p-bit product is one bit more than the n-bit multiplicand when the multiplicand is symmetric, and two bits more when the multiplicand is non-symmetric. Since the low power tap multiplier utilizes a minimal number of small unstacked transistors, it consumes less power and requires less silicon area.

Abstract: Disclosed is a method for generating psuedo-noise (PN) sequences utilizing a system comprised of a quantizer, and N directly quantized output/input map containing chaotic map cells, each in functional combination with combiner means and an m-bit shift register.

Abstract: An apparatus for computing a logarithm to a base p of a floating-point number X. The floating-point number X is represented in the format of (?1)Sx·2Ex·Mx, where Mx=(1+fx)=(1+Ax·2?K)+(Bx·2?N), where Sx is a sign, Ex is an exponent, Mx is a mantissa, 1?Mx<2, fx is a N-bit fraction, Ax is a value of the most significant K bits of fx, Bx is a value of the least significant (N?K) bits of fx, 0?K<N, and p, K, N are natural numbers. The apparatus includes: a first multiplier, a logarithmic table, a first adder, a divider, a Taylor-Series approximation circuit, a second multiplier, and a second adder.

Abstract: A carry ripple adder contains five first inputs for accepting five input bits having equal significance w that are to be summed and two second inputs for accepting two carry bits having the significance w. It also contains an output for a sum bit having the significance w and two outputs for two carry bits having the significances 2w and 4w.

Abstract: An apparatus and method are disclosed for minimizing accumulated rounding errors in coefficient values in a lookup table for interpolating polynomials. Unlike prior art methods that individually round each polynomial coefficient of a function, the method of the present invention use a “ripple carry” rounding method to round each coefficient using information from the previously rounded coefficient. The “ripple carry” method generates rounded coefficients that significantly improve the total rounding error for the function.

Abstract: A method and apparatus are used to generate FFT data addresses for a butterfly stage based upon a computation stage value. The method includes setting a selected bit of a binary word at a logical value, performing an addition operation by adding a logical “1” to the binary word, and skipping a carry bit as selected by a one-hot decoded stage value during the addition operation. The apparatus includes consecutive adders configured to store a binary value and perform an addition operation on the binary value, multiplexers configured to select either the carry out output of the current consecutive half adder or the carry out output of the previous consecutive half adder as the carry in input of a next consecutive adder, and sets of logic gates that provide one bit of the data address.