Abstract: First of all, after removing a passivation film on a failure pellet area, a timing failure level of the pellet area is digitized using a tester. Then, a polyimide solution is dropped on the upper semi-circular region of the pellet area. Then, the timing failure level of the pellet after forming the polyimide film is digitized using the tester again. Thereafter, the timing failure value after forming the polyimide film and the timing failure value before forming the polyimide film is compared. Then, based on the comparison results, the region with failure is judged. Then, repeating the step of selectively forming the polyimide film on the region with failure and the step of judging the region with failure, the failure region is identified.

Abstract: A vertically mountable semiconductor device including at least one bond pad disposed on an edge thereof. The bond pad includes a conductive bump disposed thereon. The semiconductor device may also include a protective overcoat layer. The present invention also includes a method of fabricating the semiconductor device, including forming disconnected notches in a semiconductor wafer, redirecting circuit traces into each of the notches, and singulating the wafer along the notches to form bond pads on the edges of the resultant semiconductor devices. A method of attaching the semiconductor device to a carrier substrate includes orienting the semiconductor device such that the bond pad is aligned with a corresponding terminal of the carrier substrate, and establishing an electrical connection between the bond pad and the terminal.

Abstract: A method and apparatus (10) for breaking a wafer (24) into die (26) having a high aspect ratio. In one embodiment, a multi-radii dome (12) is utilized to controllably break the wafer in two directions. The two different dome curvatures (R1, R2) provide an even, controlled, force along the kerfs in both the X-direction and the Y-direction. In another embodiment, a cylindrical dome (80) being curved (R3) in the Y-direction and flat in the X-direction is used to break a wafer into die having exceptionally high aspect ratios. The present invention reduces the likelihood of die fracture in the long dimension during the wafer break process. The wafer (24) is mounted on stretchable wafer tape (18) during the break process to prevent the die edges from contacting and rubbing with one another after the break process. The present invention allows separation of die of exceptionally large aspect ratios such as those having a 1:25 aspect ratio.

Abstract: A multi-part lead frame die assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame assembly which utilizes equipment designed for single lead frame processing. If desired, the materials for the multi-part lead frame may be dissimilar.

Abstract: Methods and apparatus pertaining to flip chip ball grid array packages are disclosed. A substrate comprises a base layer with a dielectric laminated thereon such that a cavity in the dielectric exposes the base layer. A die is then mounted to the exposed portion of the base layer. Preferably, an upper portion of the dielectric forms a frame for receiving a heat spreader.

Abstract: The specification describes techniques for applying under bump metallization (UBM) for solder bump interconnections on IC chips with Al bonding sites. The UBM of the invention comprises a copper layer applied directly to the aluminum bonding sites. Reliable bonds are obtained if the Al surface is a nascent surface. Such a surface can be provided by back sputtering an aluminum bonding site, or by a freshly sputtered aluminum layer. The copper layer is deposited on the nascent aluminum surface in e.g. a cluster tool without breaking vacuum. The UBM can be patterned using subtractive techniques.

Abstract: A method for additively de-marking a packaged integrated circuit die bearing engraved marking indicia on an exterior surface thereof. The marked surface is covered with an overlayer of material to fill the engraved markings and provide a surface suitable for re-marking. The covering material may be applied in a flowable state by applicator contact or by non-contact dispensing, or may be applied as a preformed segment. The exterior surface to be covered may be pre-treated to enhance bonding of the covering material. The covering material may be bonded to the marked surface in a post-application curing operation. De-marked integrated circuit packages are also disclosed.

Abstract: A flip-chip semiconductor device comprises a carrier substrate having a conductor pattern on at least one side and at least one semiconductor die with an active surface and an opposed ground surface. A conductive backing plate is conductively bonded to the ground surface. The active surface faces and is electrically connected to the conductor pattern of the carrier substrate. A conductive down-bond connection is provided between the backing plate and a ground connection or reference potential connection. The backing plate is preferably rigid and can be manipulated for indirect alignment of the die or dice carried thereon relative to the substrate.

Abstract: A molded plastic package incorporates a lead frame which includes a plurality of leads radially aligned around a central opening. A die is mounted in the central opening and is electrically connected to the leads by wire bonding. A molded plastic casing is formed over the die, wiring and lead frame to encapsulate the package. The lower surfaces of the die and lead frame are exposed through the package. A method for making the molded plastic package includes mounting the die and lead frame onto an adhesive tape, electrically connecting the die to the leads by wire bonding, forming a molded plastic casing over the die, wire bonding and lead frame, and then removing the adhesive tape to expose the lower surfaces of the die and the lead frame.

Abstract: A method of in-line monitoring for shallow pits formed on a semiconductor substrate using an electron beam. The electron beam is scanned across exposed pads on the semiconductor substrate and relative concentrations of secondary electrodes are examined to identify shallow pits.

Abstract: A semiconductor device soldered to a conical mounting pedestal of a metal substrate reduces the lateral shearing stress created by temperature changes. An angle between the bonding surfaces of the semiconductor device and the metal substrate can be selected as a function of the coefficients of thermal expansion of the device and substrate material.

Abstract: First of all, after removing a passivation film on a failure pellet area, a timing failure level of the pellet area is digitized using a tester. Then, a polyimide solution is dropped on the upper semi-circular region of the pellet area. Then, the timing failure level of the pellet after forming the polyimide film is digitized using the tester again. Thereafter, the timing failure value after forming the polyimide film and the timing failure value before forming the polyimide film is compared. Then, based on the comparison results, the region with failure is judged. Then, repeating the step of selectively forming the polyimide film on the region with failure and the step of judging the region with failure, the failure region is identified.

Abstract: A method and system for fabricating lamp tiles which include a molded body and a plurality of electrically conductive leads protruding therefrom. The lamp tiles are made by overlaying an anode lead frame having anode leads, on a cathode lead frame having cathode leads, and then depositing molding material on intersected anode and cathode leads. The lamp tiles are manufactured in an assembly line process which includes a feeder to feed the anode and cathode lead frames and a molder to deposit the molding material.

Abstract: Methods of forming flip chip bumps and related flip chip bump constructions are described. In one implementation, a bump of conductive material is formed over a substrate. At least a portion of the bump is dipped into a volume of conductive flowable material, with some of the flowable material remaining over the bump. The remaining flowable material over the bump is solidified and includes an outermost surface the entirety of which is outwardly exposed. In another implementation, the outermost surface include an uppermost generally planar surface away from the substrate. The solidified flowable material together with the conductive material of the bump provide a bump assembly having a height which is greater than the height of the original bump. The increased height is achieved without meaningfully increasing a width dimension of the bump proximate the substrate.

Abstract: A microelectronic assembly (10) includes a printed circuit board (12) that includes a substrate (14) having a die attach region (22) and a plurality of first bond pads (24) disposed and spaced apart at the die attach region (22). A channel (26) effective in improving fluid flow extends across the die attach region (22) apart from the first bond pads (24). An integrated circuit die (16) is mounted onto the printed circuit board (12) and includes a major face (28) facing the substrate (14) and spaced apart therefrom by a gap (30) and second bond pads (25) disposed on the major face (28) in a pattern such that each of the second bond pads (25) registers with a first bond pad (24). Solder bump interconnections (18) connect the first bond pads (24) to the second bond pads (25). Encapsulant (20) is disposed within the gap (30) and flows over the substrate (14) and the channel (26) to encapsulate the solder bump interconnections (18).

Abstract: An electric field changing in the form of a ramp waveform with the passage of time is applied to an oxide layer, and the electric current densities applied to the oxide layer at measuring points of time are measured. The electric current densities applied until the oxide layer is broken down, are integrated with respect to time, thus obtaining a total electric charge amount Qbd used up to the breakdown of the oxide layer. The total electric charge amount Qbd is divided by each of the electric current densities at the measuring points of time, thus obtaining each of the estimated values of oxide layer lifetime at the time when it is supposed that each of the electric current densities at the points of time was constantly applied. Using the field intensities and the lifetime estimated values at the common measuring points of time, there is determined a regression line in which the oxide layer lifetime estimated values are expressed in the form of a function of the field intensities.

Abstract: A method for populating an substrate (14) with particles (12, 16), comprising the steps of applying an adhesive coating (22) to both surfaces of a substrate (14) and loading the particles (12, 16) to the adhesive areas (30) of the adhesive coating (22), such that each surface of the substrate (14) is fully populated with the particles (12, 16) which may thereafter be reflowed simultaneously. The particles may be composed of a variety of compositions, including copper, other metals, alloys, and synthetic resin compounds, such as conductive plastics.

Abstract: An electronic semiconductor device package, the package having: a substrate having a top and bottom surface and having traces; a die attached to the top surface of the substrate; first level interconnects of the die to the traces of the substrate; encapsulant which covers the die and first level interconnects; and a lid attached to the encapsulant, wherein the lid comprises at least one lid support which extends from the lid to the substrate.

Abstract: In a method for eliminating residual oxygen contaminations from crucible-drawn silicon wafers, a number of trenches are etched into the front side of a crucible-drawn silicon wafer and that the silicon wafer is subsequently tempered at approximately 1100.degree. C. As a result of the extremely large surface area in the front side of the silicon wafer, oxygen contaminants can effectively diffuse out. After the oxygen drive-out has ensued, the trenches are filled bubble-free with epitaxially deposited silicon and the active structures are processed into the front side.

Abstract: Two kinds of first and second adhesive components 8a, 8b are used to a joining treatment for connecting a protruded electrode 6 of a semiconductor element 5 and a substrate wiring 3 of a wiring substrate 1. The first adhesive component 8a is at a central portion on the surface of the semiconductor element 5 to be joined with the wiring substrate, in which the first adhesive component 8a is formed, and the second adhesive component 8b is disposed in a region at the periphery thereof having the protruded electrode 6. Further, the cure-shrinkage of the first adhesive component 8a is made greater than that of the second adhesive resin 8b and the modulus of elasticity of the second adhesive component 8b is made greater than that of the first adhesive component 8a such that the thermal expansion of the second adhesive component 8b in the high temperature circumference does not exceeds the cure-shrinkage during curing of the first adhesive 8a.