Abstract: First interconnect lines each having an electric capacity given by C and second interconnect lines respectively adjacent thereto are formed on an upper surface of an insulating film. The first interconnect lines and the second interconnect lines are electrically isolated from a substrate and are electrically floating. The second interconnect lines are connected to a third interconnect line. As a result, the second interconnect lines and the third interconnect line which are electrically connected to each other as a whole have an electric capacity given by 12C. The first interconnect lines are irradiated with charged particles. The difference in the amount of secondary electrons emitted from the first interconnect lines depending on the magnitude of the electric capacity is detected as a potential contrast and used to evaluate whether or not there is contact between the first interconnect lines and the respectively associated second interconnect lines.

Abstract: Disclosed is a packaging method of semiconductor device comprising the following step, preparing a PCB or BGA substrate with array-typed dam formed thereupon; placing a plurality of semiconductor devices into the array-typed dam, and attaching each semiconductor devices onto the dam grid; wire-bonding the semiconductor devices; performing lid-covering or resin-sealing process. The present invention forms the dam structure necessary for the package by an off-line process, and then attaches the dam structure on the substrate. Therefore, the problems of damage of PCB or substrate and short circuit due to the high-temperature and high-pressure pressing process can be prevented, moreover, the yield and the reliability can be enhanced.

Abstract: A method of padding an electronic component, mounted on a flat substrate, with a fluid filler, in which the fluid filler that is applied in a tight-fitting manner to the electronic component mounted on the substrate. The arrangement composed of substrate and electronic component is then heated. The substrate is provided with at least one through orifice in the area of the electronic component prior to applying the filler. The filler is applied at the end of the through orifice facing away from the electronic component.

Abstract: A method of fabricating bond pads on a semiconductor device which includes providing a semiconductor device having a surface. A coating of solderable electrically conductive metal is deposited on the surface, preferably by sputtering, and portions of the coating are selectively removed by ablation or vaporization, preferably by use of a laser beam. The selective removal is accomplished by selective movement of the laser relative to the coating or by use of a mask followed by traversal of the laser beam over the entire coating. The coating is preferably a 500 angstrom layer of chromium over which is a 1500 angstrom layer of palladium followed by a 3500 angstrom layer of gold.

Abstract: Chip-like stacks of thinned chips are mounted in wells etched into a substrate. A "chip-like" stack is a stack of chips, which in the aggregate have a height approximately equal to that of a single conventional chip. These chip-like stacks are mounted in a variety of packages. In a preferred embodiment, the stacks are mounted in wells within the substrate of an integrated circuit and the stack is provided with a patterned overlay so that all the circuit connections can be made from the upper surface of the stack. The patterned overlay is protected by a planar insulator. A plurality of substrates may be stacked, one upon the other.

Abstract: A method of water mark inspection. By forming a pattern on a test wafer, the water mark formed thereon directly reflects the features of a wafer product to be evaluated. The water mark is formed by simulating fabrication process conditions of forming the wafer product of which the performance is to be evaluated. Thus, after scanning the water mark by a defect inspection machine, the performance of the wafer product is evaluated.

Abstract: A method for producing integrated circuit devices including the steps of producing a plurality of integrated circuits on a wafer having first and second planar surfaces, each of the integrated circuits including a multiplicity of pads, waferwise attaching to both said surfaces of the wafer a layer of protective material, thereafter partially cutting into the wafer and the protective material attached thereto, thereby to define notches along outlines of a plurality of prepackaged integrated circuit devices, forming metal contacts onto the plurality of prepackaged integrated circuit devices while they are still joined together on the wafer, at least a portion of said metal contacts extending into the notches and thereafter separating the plurality of prepackaged integrated circuit devices into individual devices. Integrated circuits produced according to the method are also disclosed and claimed.

Abstract: In a lead frame carrying method and apparatus, first and second press units are provided on sides of a pair of carrier rails. When carrying a lead frame along the carrier rails, a side edge portion of the lead frame is clamped by being pressed from a surface and a back face of the lead frame almost perpendicularly thereto by the first and second press units. In the lead frame, the clamped side edge portion is floated by a predetermined height above one of the carrier rails during carrying. Accordingly, the lead frame can surely be clamped and carried. In addition, when carrying the lead frame along the carrier rails, the lead frame is damaged with difficulty by the carrier rails.

Abstract: The present invention relates to a stacked bottom lead package in semiconductor devices and a method thereof. More specifically, comprising leads that are bent along with the circumference of the body which has been premolded, wherein a chip is include inside the premolded body. The package and the method thereof according to the present invention enable a dual process, decreasing solder fatigue of the lead by carrying heat via the extended leads and emitting the heat out of the chip, and decreasing the area required for stacking semiconductor packages.

Abstract: An integrated electro-optical package including a dual sided opto-electronic device, composed of a substrate with an array of light emitting devices (LEDs) formed on a first major surface thereof, and at least one vertical cavity surface emitting laser formed on an opposed second major surface of the substrate. A mounting structure formed so as to allow for the mounting of the dual sided opto-electronic device on the interior major surfaces, and further having electrical conductors for cooperating with the LEDs and VCSEL of the opto-electronic device. A driver substrate having electrical connections for interfacing with the mounting structure and the dual sided opto-electronic device. A plurality of driver circuits connected to the mounting structure and dual sided opto-electronic device through connection pads formed on the driver substrate.

Abstract: A method for connecting substrates includes using an adhesive interposer structure (11) to bond a semiconductor device (26) to a substrate (18). The adhesive interposer structure (11) includes a non-conductive adhesive laminant (12) and conductive adhesive bumps (13). The conductive adhesive bumps (13) provide a conductive path between conductive bumps (27) on the semiconductor device (26) and conductive metal pads (21) located on the substrate (18). In an alternative embodiment, a conductive adhesive material (34) is screen or stencil printed into vias (39) located on a printed circuit board (38) to form conductive adhesive bumps (33). A non-conductive adhesive (52) is then screen or stencil printed onto the printed circuit board (38) adjacent the conductive adhesive bumps (33). A semiconductor die is then connected to the structure.

Abstract: There is a trend in the electronics industry towards a preference for components that can be surface mounted on a carrier, such as a circuit board. By using surface mountable leads on a component together with a "Single-In-Line" technique it is possible to surface mount a component (5) upstanding on a circuit board (7) with the component leads surface mounted on the board. The leads (8) may be bent at their bottom extremities and provided with feet (10) for effective contact with the board. Guide and support pins may be used to hold the component in position during mounting and connecting the component and to brace the leads on the component when mounted on the board.

Abstract: A jig for a fusion bonding process includes a sealable chamber having a first station for a first wafer and a second station for a second wafer. The wafers are initially separated from each other while a vacuum is created in the chamber. In one embodiment of the invention, movably mounted spacers separate the wafers while the vacuum is formed. The spacers are then moved to allow the wafers to come into contact and form an initial bond. In another embodiment, wafers in the first and second stations are tilted away from each other so that gravity keeps the wafers separated while the vacuum is formed. After the vacuum is formed, the chamber is rotated so that gravity pushes the two wafers together. In either embodiment, a mechanical pushing system or vibrational energy can apply force to induce or improve the initial bond. The initial bond seals cavities formed between the wafers.

Abstract: An encapsulated integrated circuit package uses a heat dissipating dam which is secured about the die to the die support. A dam constrains the outward movement of liquid glob top material during the manufacturing process. In addition, the dam provides heat dissipating properties for the integrated circuit package and may improve the structural integrity of the package as well. The dam may be efficiently applied to the die support using automated techniques, such as adhesive tape bonding.

Abstract: A thin film forming apparatus includes a specimen holder on which a substrate for thin film formation is placed, a transfer plate opposing the specimen holder, on which a sheet film having a thin film formed on a surface is placed, a thin film forming chamber comprising the specimen holder and the transfer plate, a pressure unit for moving at least one of the specimen holder and the transfer plate and pressing the specimen holder against the transfer plate for a predetermined time while the substrate and the thin film formed on the sheet film are in contact with each other, a heating unit for heating the substrate at a predetermined temperature, and an exhausting unit for vacuum-exhausting the thin film forming chamber.

Abstract: A fabrication method for a chip package includes the steps of forming a first substrate having embedded leads, forming a second substrate with embedded leads and a central aperture therethrough, and attaching the second substrate to the first substrate to form a substrate with a recess for receiving a chip. A chip may then be mounted within the central aperture of the second substrate, on the first substrate, and bond pads of the chip may be attached to leads exposed on one of the first and second substrates with a plurality of metal wires. A resin may be molded over the device to protect the metal wires, the chip, and the leads.

Abstract: In a lead frame flash removing method and apparatus, a lead frame is molded integrally with a case. After molding, abrasive agent-mixed water is sprayed to a surface of the lead frame where a flash is formed. The lead frame is dipped in an electrolytic solution and applying a DC voltage is applied across the lead frame and an electrode in the electrolytic solution, thereby electrolytically processing the lead frame. After the electrolytic process, an external force is applied to the surface of the lead frame, thereby removing the flash.

Abstract: The invention includes the use of a decal to produce a packaged chip either at the chip level or wafer level. The decal includes a substrate containing circuitry that routes the chip output pads to bumps prepared for package attachment to another substrate such as a printed circuit board. The decal can be applied either to the wafer or to a single chip. The decal protects the chip and if necessary changes the interconnection density so that the chip can be interfaced with a printed circuit board or other electronic device. This configuration also may allow the packaged integrated circuit to be tested utilizing the bumps on the decal as temporary electrical contact features.

Abstract: A method of forming a semiconductor device having a semiconductor chip having electrodes on which electrode pins are formed includes the steps of forming a complex having the electrode pins fixed in a fixing member, an arrangement of the electrode pins corresponding to that of the electrodes, connecting the electrode pins with the electrodes by mounting the complex on the semiconductor chip, and removing the fixing member from the complex mounted on the semiconductor chip.

Abstract: A ceramic multilayer circuit and a method for manufacturing a ceramic multilayer circuit which has economical, corrosion-resistant external contacts or external conductor paths that are immune to the Kirkendall effect and can be utilized for different mounting processes. The circuit structure and the method involve the use of a pure silver paste to implement external conductor paths or external contacts. Corrosion resistance is ensured by a thin metallic protective layer.