Abstract: A semiconductor integrated circuit device according to the present invention comprising an electric circuit formed in a semiconductor substrate, said circuit including first and second nodes between which a potential difference is provided, a wiring of a large ground capacitance connected to the first node, and a bypass capacitor connected to the second node, said wiring and bypass capacitor being of an integral structure prepared by laminating an upper conductor film pattern connected to the second node via an insulating film on a lower conductor film pattern connected to the first node. A MIM-structure in which a wiring and a bypass capacitor are made integral is employed in the semiconductor integrated circuit device of the present invention, making it possible to eliminate the large area required for forming the independent bypass capacitor. Also, the ratio of the ground capacitance of the wiring to the capacitance of the bypass capacitor is constant regardless of the change in the length of the wiring.

Abstract: An improved architecture for programming an output cell (macro cell) in a PLD. The memory cells for the macro cell are stored in the main array itself. Upon power-up, a power-on sense circuit senses the presence of power and enables an architecture portion of the main array while disabling the rest of the main array. The power-on sense signal also enables a path from the output of the array to the macro cell elements to be programmed. When the power-on sense signal is removed a short time after power-up, this path is blocked so that the array outputs continue on their normal path and the architecture portion of the array is disabled while the rest of the array is enabled for normal operation.

Abstract: A CMOS programmable logic array includes a logical AND plane receiving a first group of input logic signals for forming a second group of logic minterms, and a logical OR plane receiving the logic minterms for forming a third group of output logic signals. Each type of logical plane contains a plurality of logic gates. Each plane type can be formed from the other plane type by the addition of a logic inverter to each input, and output of, that other-type plane. Interconnections determine the combination of input signals used to define the logic equation of the signal at the output of each logic gate of each plane. Static latches are used to retain the states of input and minterm logic signals. Logic planes and latches can be operated responsive to a two-phase clock signal.

Abstract: A programmable logic array (PLA) is described, having an integral decoder for selecting individual product lines. The integral decoder receives an input address by way of a set of buffers, which can be disabled so as to disable the integral decoder in normal operation. The buffers can be tested in their disabled state by means of an extra product line and extra output line. The extra product line is coupled to all the bit lines and to the extra output line, but not to any of the other output lines; the extra output line is coupled to the extra product line, but not to any of the other product lines. The buffers are tested by applying a sequence of addresses to the buffers in their disabled state, and observing the extra output line.

Abstract: A programmable logic array (PLA) is tested by applying a sliding-ones pattern to the bit lines from a circular shift register, and individual product lines are selected by applying a sequence of addresses from a linear feedback shift register (LFSR) to an integral decoder. Both the circular shift register and the LFSR are controlled by a common clock signal, avoiding the need for special synchronizing logic between them. The sequence lengths of the circular shift register and the LFSR are chosen to be coprime numbers. Thus, after a predetermined number of clock beats, all the crosspoints in the AND plane will have been individually tested.

Abstract: An output circuit device according to the present invention comprises first circuit means (1) having a first type MOS transistor and a second type MOS transistor connected in parallel to each other, second circuit means (3) having at least a first type MOS transistor and a second type MOS transistor connected in parallel to each other, and a load capacitor means (13) connected between the output terminal and the ground potential for charging and discharging electric charge of an output signal.The source of said first type MOS transistor is connected to a first power supply and the source of said second type MOS transistor being connected to a second power supply.The second circuit means is connected between the output of said first circuit means and an output terminal. The source of the first type MOS transistor in the second circuit means is connected to the first power supply. The source of the second type MOS transistor is connected to the second power supply.

Abstract: A logic circuit comprises at least one signal input terminal, an output terminal, an output circuit including a first bipolar transistor coupled between the output terminal and a reference potential terminal, to discharge the output terminal, and an MOS type logic circuit for supplying to the base of the first bipolar transistor a signal of a level corresponding to an input signal supplied to the at least one signal input terminal. The logic circuit further comprises a control MOS transistor coupled between a power source terminal and the base of the bipolar transistor, for supplying part of the base current to the bipolar transistor in response to a signal at the output terminal.

Abstract: An AND gate (40) includes first and second input leads (42,43) and an output lead (44). The AND gate includes a first N channel MOS ("NMOS") transistor (58) which couples the output lead to ground in response to the signal (IN1) on the first input lead and a second NMOS transistor (60) which couples the output lead to ground in response to the signal (IN2) on the second input lead. A buffer (76) having a high output impedance is coupled to the output lead and tends to maintain the output lead in a constant state. When the signal on the first input lead goes high, the first NMOS transistor turns off and a PMOS transistor (64) turns on, thereby coupling the output lead to a high voltage source for a predetermined time period. If the second NMOS transistor is off, the resulting pulse causes the AND gate output signal (Vout) to go high. The high impedance buffer maintains the output lead in the high state.

Abstract: An output buffer includes a pull-up transistor (N1), a first pull-down transistor (N3), a second pull-down transistor (N8), and a logic circuit (15). The logic circuit (15) is responsive to a data input signal making a high-to-low transition and the output signal making a high-to-low transition for maintaining the second pull-down transistor (N8) turned-off until after an output node has made the high-to-low transition, thereby reducing significantly the ground bounce noise.

Abstract: A programmable logic array device basically comprising a programmable AND gate array (FIGS. 5, 11) having addressable rows (40-45) and columns (32-38) or memory cells (30, 31) which can be individually programmed to represent logic data; an input signal receiving circuit (FIG. 9) for developing a corresponding buffered input signal; a first row driver (FIG. 10) responsive to the buffered signal and operative to cause a particular row of memory cells in an AND array (FIG. 11) to output corresponding logical product of AND-input signals, OR/NOR sensing circuitry (FIG. 12) for sensing the AND array product signals and for developing therefrom corresponding logical OR sum signals; circuit means output terminal circuitry; output switching circuitry (FIG. 14) responsive to a control signal and operative to couple either the circuit means output signal or a registered (FIG. 13) output to a device input or output terminal (FIG.

Abstract: A bipolar transistor-complementary field effect transistor composite circuit is provided which includes a pair of first and second bipolar transistors each having a collector of a first conductivity type, a base of a second conductivity type and an emitter of a first conductivity type. Collector-emitter current paths of the bipolar transistors are connected in series to each other between first and second potentials, with a connection node providing an output of the composite circuit. Field effect transistors are respectively coupled between the bases and collectors of the bipolar transistors for controlling the on-off states of the bipolar transistors in opposite relationship to one another in response to an input signal provided to the composite circuit. Also, discharge arrangements are provided for the bases of the first and second bipolar transistors to discharge parasitic capacitance in the bases of the first and second bipolar transistors when they are turned off.

Abstract: The blocking circuits which, during precharge, inhibit the data passage to the AND and OR planes of a dynamic programmable logic array with NOR-NOR structure, implemented in C-MOS technology, comprise a pair of transistors with complementary channel doping, the first of which controls the signal passage to the AND or the OR plane, respectively, and the second inhibits the gates of the respective plane during precharge.

Abstract: A circuit for coupling ECL level logic signals to NMOS circuitry first translates the ECL logic swing from the range of -1.6 v to -0.8 v up to the range of about +0.5 v to +1.3 v. This is done by driving the source of an enhancement device with the ECL input signal. This has the further benificial effect of compensating for temperature changes and process related variables. The level shifted signal is then applied to a gain stage for amplification and delivery to the using circuits. If the ECL input signal is available in complementary form then the complement can be used to drive the source of the gain stage; otherwise it should be connected to V.sub.ref of the ECL circuitry.

Abstract: A programmable logic array 100 which uses parallel transistor logic gates 150 arranged in a compact layout for fast signal propagation. One of logic planes 120 or 130 is prechargeable to substantially reduce power consumption using a simple, one-phase clock.

Abstract: A programmable logic device includes an AND plane and an OR plane associated with the AND plane. At least one of the AND and OR planes includes an array of programmable memory elements which can be selectively programmed to define a desired logic function. In one form, a function cell designed for providing one of a predetermined functions, such as a counter or shift register function, selectively is provided. In another form, a driver circuit connected to a pair of input lines has a first state in which one of the paired input lines serves as an inverting input line and the other as a non-inverting input line and a second state in which both of the paired input lines are set at low level. In a further form, two pairs of input lines of the AND plane are connected to an input or input/output terminal of the device.

Abstract: A CMOS buffer receiver is provided for converting TTL or CMOS input voltage signals to CMOS signals so as to drive CMOS loads on VSLI chips. The buffer receiver comprises a reference voltage generator coupled to a compensation network having an output signal which varies with process, temperature and voltage supply. The compensated output signal is coupled to the gates of any number of current source load transistors of a plurality of series connected transistor pairs which comprise individual stabilized input converters all of which have their switchpoint located in the middle of their characteristic curves so that their switchpoints are immune to process, temperature and supply voltage variations.

Abstract: A circuit for charging a capacitive load such as a data or address bus in a VLSI circuit includes a voltage source input, a PFET switch connected between the voltage source input and the capacitive load or bus, and a voltage regulator connected to the capacitive load and to the gate of the PFET switch to cause the switch to conduct during a predetermined time only if the voltage on the capacitive load is less than a predetermined voltage, and to disconnect the capacitive load from the voltage source input when the voltage on the capacitive load reaches or exceeds that predetermined voltage level. The voltage regulator may include a first inverter having its input connected to the bus and a second inverter having an input connected to the output of the first inverter and having an output connected to the control input of the switch. The first inverter is constructed to output a low level when the voltage on the first inverter input is at or above the designated predetermined voltage.

Abstract: A high-speed CCD clock driver circuit is obtained by coupling a plurality of driver circuits in parallel, with each driver circuit including a short circuit protection circuit consisting of the parallel connection of a resistor and a diode. In a further embodiment, a plurality of pre-driver circuits are connected in parallel to provide drive to the parallel-connected driver circuits.

Abstract: A programmable logic circuit which can be implemented on a single integrated circuit in conjunction with other associated circuitry. The circuit includes programmable fuses whereby the circuit can be programmed to implent AND, NAND, OR, or NOR functions. Additionally, the circuit can be programmed to accept either a high or low true logic on each individual input as well as providing either a high true or low true output.

Abstract: A masterslice cell wireable to form any of a selected book set of two level differential cascode current switch basic circuits. Twenty percent increased performance is provided as compared with ECL masterslice circuits running at the same power. In spite of increased wire due to differential logic, and potential increased complexity in design software, the invention is actually readily adaptable to existing masterslice design systems.