Abstract: In the present invention, an improved synchronous PLA circuit is disclosed. The PLA circuit is responsive to a single clock cycle. The PLA circuit has no internal or output glitches. Further, the PLA circuit uses less power since there are no internal or output glitches. The PLA circuit requires less area since metal lines do not have to carry as much power and do not have to be as wide as the prior art PLA circuits. Since less power is used, long term reliability is improved due to reduced heating stress and reduced current density stress (metal electromigration, etc.). The PLA circuit consists of two logic arrays and four dummy signal delay lines. When a clock signal gates the input signals into the logic array, it also simultaneously generates a dummy signal. The dummy signal propagates through adjacent dummy signal delay lines that parallel each logic array dimension and match the longest or worst case, delay through the logic array.

Abstract: A programmable logic array (100) includes a set of input terms which are programmably coupled to a first set of AND gates (102-1) through 102-66). The output signals from the first set of AND gates are programambly electrically connected to a second set of AND gates (104-1 through 104-66). The second set of programmable AND gates enhances flexibility of design and permits product terms with a larger number of factors to be generated. The output leads from the second set of AND gates are programmably electrically coupled to a first set of OR gates (106-1 through 106-22) which in turn are programably electrically coupled to a second array of OR gate logic (108-1 through 108-10). This also permits greater design flexibility. The output terms from the second set of OR gate logic can then be used to generate the output signals from the programmable logic array (100). In addition, a bus (110) is programmably electrically coupled to each of the output signals from the second OR logic array and the output signals (O.

Abstract: A CMOS current sense amplifier is composed of an output inverter gate, a combined driver and biasing stage that biases the output inverter gate and drives its transistors, and an input stage that acts to reduce the input voltage swing. The circuit responds rapidly to input current changes and is therefore useful in sensing the currents in large memory arrays that have large shunt capacitance values.

Abstract: A decoder circuit for fully decoding N input variables includes 2.sup.N logic gates arranged into 2.sup.N-1 pairs of gates, with each gate having N inputs, and one output. The decoder also includes (N-1) inverters for producing the complements of N-1 of the N input variables whereby the (N-1) input variables and their complements are arranged into 2.sup.(N-1) different combinations of (N-1) signals for generating a different combination of (N-1) signals per pair of logic gates. (N-1) inputs of each of the two gates forming a pair of gates are interconnected to receive the same N-1 input signals forming one of the 2.sup.N-1 combinations. The Nth input variable is applied to the Nth input of one gate from each pair of gates and the output of the one gate from each pair is connected to the Nth input of the other gate with which it is paired.

Abstract: A sense amplifier for a programmable read only memory having a sense current source circuit for supplying memory cells in the memory with currents. The sense current source circuit is adapted to supply memory cells with a cell current for both a regular reading and a verify reading. A reference value of the cell current for the regular reading is selected to be higher than a reference value of the cell current for the verify reading, whereby a sufficient value of margin of voltage of a power source for the memory is ensured.

Abstract: A programmable array logic device including a programmable logic array, at least one register pair, a multiplexer coupled to the register pair so that they can share a common I/O pin, and an observability buffer for controlling the multiplexer. A dual clock buffer is provided so that registers within the register pair can be clocked singly when in a preload mode or together when in a logic or verification mode. When in the logic mode, either the output of a buried state register or an output register is observed at the I/O pin under the control of a product term generated by the logic array. When in the preload mode the register to be preloaded is selected by an externally provided preload select signal. In the verification mode, which typically follows a programming mode, individually selected product terms within the logic array can be observed by clocking them into the register pairs.

Abstract: A semiconductor IC device has word lines which are sequentially arranged and each connected to the gate of a MOS transistor such that its drain and source are individually connected to the adjacent word lines. Either of these adjacent word lines is connected to a fixed potential source such that potential changes in selected one of these word lines are electrically shielded and do not affect the non-selected other word lines in the device.

Abstract: This invention provides a refresh operation control circuit for a semiconductor memory device. Two flip-flop circuits respectively temporarily hold a normal read start command signal and a refresh start command signal generated within the memory device. A normal operation/refresh operation priority determining circuit wherein 2-input logic circuits are cross-connected so that one output in each case of each of these two flip-flop circuits provides one input of the other flip-flop circuit. The priority determining circuit determines the priority of normal read operation and refresh operation in accordance with the logic level relationship of the one inputs. Either control of the start of normal read operation or control of the start of refresh operation is carried out in accordance with the output of this determination.

Abstract: A binary threshold comparator is disclosed for first and second binary numbers, wherein the first is variable and the second is a threshold or reference, with the complement of the second number available. The comparator may be a high threshold (greater/equal) comparator or a low threshold (less/equal) comparator. It comprises 5 MOSFETs per bit stage, with two additional MOSFETs per comparator for high/low determination and carry in precharge. A particular multi-bit embodiment of the comparator has a modified most significant bit stage which provides a complement of the normal output when the most significant bits of the numbers to be compared are different to prevent an immediate reversal of comparator output when a counter containing the variable number rolls over from all ones to all zeros or vice versa.

Abstract: The disclosure relates to an STL bipolar buffer/driver circuit having a low output impedance for driving capacitive leads and the like wherein the output resistor of the prior art circuits is replaced by an NPN bipolar transistor and a further circuit including a series resistor, schottky diode and schottky clamp transistor for controlling the two output transistors.

Abstract: In the buffer circuit for an integrated circuit according to this invention a load MOS transistor and a drive MOS transistor are connected in series between a power source potential node and a ground potential node of the integrated circuit. A constant current circuit means connected in series with a circuit including the load MOS transistor and the drive MOS transistor.

Abstract: A level selectable FET voltage generation system is described. The system includes a single charge pump controlled by multiple feedback paths and a powerdown circuit. Each feedback path contains a capacitor divider network, a sense amplifier with a compensating voltage reference and a timer which periodically resets the capacitor divider network to insure sensing accuracy. The powerdown circuit and a selected feedback path provides a desired voltage level at the output of the charge pump.

Abstract: A coincidence decision circuit includes a plurality of data inputs and at least one coincidence decision output. This circuit comprises a plurality of coincidence detection circuit each having a plurality of inputs connected to a corresponding number of data inputs selected from the data inputs of the circuit. Each of the coincidence detection circuit is selectively put in an operable condition in response to a given selection signal so as to generate an coincidence detection signal. A circuit is connected to the coincidence detection circuit to respond to a timing signal to read out the coincidence detection signal from the coincidence detection circuit put in the operable condition. Further, another circuit is connected to the read out circuit to output the coincidence detection signal at a predetermined timing.

Abstract: The present invention is an Exclusive-OR circuit which uses a minimum number of components and which is particularly adapted for use as a building block for a parity checking circuit. The circuit only uses CMOS gates to reduce the number of included transistors.

Abstract: A method and apparatus are disclosed which provide for the generation of a trigger signal responsive to the detection of a plurality of selected sequential events in a single monitored signal. A plurality of trigger detect devices operate independently to monitor a signal for the occurrence of selected trigger criteria, and produce indications thereof having selected durations. The duration of the indications function to provide continuous indications of the occurrence of the selected trigger conditions over the periods thereof. In one embodiment, a state machine delays each of the indications by an amount of time approximately equal to the time between the respective events and a final event in the sequence, thereafter combining the indications according to preselected logical operations. As a result of the delays, the indications from the trigger detect devices are combined at approximately the same time.

Abstract: A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.

Abstract: A CMOS power-on reset circuit furnishes a reset signal for bringing the components of a circuit to a defined initial state when the common supply voltage is turned on. The output signal of the reset circuit assumes a first constant value as soon as the supply voltage rises above the level required to turn on the pulldown transistor of an initializing inverter in the reset circuit. A delay circuit causes the output signal of the reset circuit to remain at the first constant value for a period of time sufficient to allow the components of the circuit to settle. The output signal of the reset circuit is then forced to a second constant value. The reset circuit is suitable for use with power supply voltages which rise very rapidly or with power supply voltages which rise very slowly (DC sweep).

Abstract: A BIFET logic circuit for quickly switching an output line from a high level to a reference level. The BICMOS circuit comprises a push-pull circuit including a first bipolar transistor for driving current into an output line, and a second bipolar transistor for sinking current from the output line; a CFET logic circuit for performing a logic function and including at least one N type FET for providing current to the base of the second bipolar transistor when a set of input lines to the CFET circuit has a first set of predetermined values; and a resistive means for connecting one of the source or drain of the at least one NFET to a power supply to provide a source of base current to the second bipolar transistor, even when the output line drops in voltage. This circuit is especially advantageous for driving low threshold CFET circuits.

Abstract: A programmable logic array has a plurality of column units aligned parallel to each other. Each column unit consists of at least one MOSFET column, and at least one load element aligned vertically. Each MOSFET column has a plurality of MOSFETs aligned vertically. The MOSFETs have at least one common gate electrode. The MOSFETs belonging to two parallel MOSFET columns have a common linear source electrode.

Abstract: A half adder includes a first drive stage having an input and connected at its output a carry output and a second drive stage having an input and connected at its output to an addition data output. Further, a circuit is provided to precharge the inputs and the outputs of the first and second drive stages at a first timing so as to put these drive stages in a first logic condition, and then to put these drive stages in an operable condition at a second timing later than the first timing. A first logic stage is connected to a data input and a carry input, respectively, so as to generate a first logical signal to the inputs of the first and second drive stages, when the data input and the carry input assume a first logic level, thereby to put the drive stages in a second logic condition opposite to the first logic condition. Futhermore, a second logic stage is connected to the output of the second drive stage and having inputs connected to the data input and the carry input, respectively.