Patents Examined by Dac V. Ha
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Patent number: 12375330Abstract: In one embodiment, an apparatus includes a circuit to: modulate a symbol with a sequence; extend the modulated symbol to obtain a plurality of modulated symbols; and perform, on the plurality of modulated symbols, a plurality of operations according to a Recipe of operations, to obtain extended and modulated symbols. The apparatus may further include a radio frequency (RF) front end circuit coupled to the circuit to process and transmit the extended and modulated symbols.Type: GrantFiled: March 31, 2023Date of Patent: July 29, 2025Assignee: Silicon Laboratories Inc.Inventor: Fabrice Christophe Olivier Portier
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Patent number: 12375339Abstract: Spurious signals in a receiver are rejected using a method of correcting amplitude and phase imbalances in the received signal. A system implementing the method can be built into the receiver or can be used during assembly of the receiver.Type: GrantFiled: November 3, 2023Date of Patent: July 29, 2025Assignee: Associated Universities, Inc.Inventor: Matthew William Schiller
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Patent number: 12375135Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may generate a recommendation for a first codebook that is for a single transmit receive point (TRP) and that does not include a time domain (TD) or Doppler domain (DD) basis, or for a second codebook that is for multiple TRPs or that includes a TD or DD basis. The UE may transmit the recommendation. Numerous other aspects are described.Type: GrantFiled: January 31, 2023Date of Patent: July 29, 2025Assignee: QUALCOMM IncorporatedInventors: Kiran Venugopal, Wooseok Nam, Junyi Li, Tao Luo
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Patent number: 12368616Abstract: A receiver includes a voltage-to-time converter configured to sequentially output a first converted signal and a second converted signal based on a first signal, a second signal, and a time difference; a first time comparator configured to determine a first bit value based on a first first-arrival signal (FAS) and output first data including the first bit value; a delay time generator configured to select a non-target signal and a target signal based on the first bit value and from among the first converted signal and the second converted signal; and a second time comparator configured to determine a second bit value based on a second FAS and output second data including the second bit value.Type: GrantFiled: December 6, 2023Date of Patent: July 22, 2025Assignees: SAMSUNG ELECTRONICS CO., LTD., NANYANG TECHNOLOGICAL UNIVERSITYInventors: Jueon Kim, Taehyoung Kim, Donghyun Yoon, Myoungbo Kwak, Jaewoo Park, Youngdon Choi, Junghwan Choi
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Patent number: 12368468Abstract: In order to eliminate the reliance of ultra-high bandwidth (UWB) standalone transceivers and narrow-band-assisted (NB-assisted) UWB transceivers on BLUETOOTH™ (BLE) usage, an NB radio may be used. The NB radio may be tightly coupled with the UWB radio, for example driven by the same time source, to enable leveraged use of ACP (Acquisition Packet) for discovery, session setup, and maintenance over UWB and/or NB-assisted UWB without the use of BLE. Rules for advertising ACP and scanning for ACP may be defined for two modes of operation. An ad-hoc discovery may be based on external acquisition triggers, while a managed discovery may be based on an ongoing discovery advertisement process. ACPs may thereby be transmitted over UWB and/or NB.Type: GrantFiled: September 22, 2023Date of Patent: July 22, 2025Assignee: Apple Inc.Inventors: Lochan Verma, Yong Liu, Robert Golshan
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Patent number: 12362972Abstract: Proposed is a device for receiving a four-level pulse amplitude modulation (PAM-4) signal, which includes a first comparator for comparing a received PAM-4 signal with a predetermined threshold voltage to output a most significant bit (MSB) signal; and a second comparator for comparing the differential signal difference between the positive signal and negative signal of the received PAM-4 signal with a reference voltage to output a least significant bit (LSB) signal.Type: GrantFiled: January 23, 2024Date of Patent: July 15, 2025Assignee: Foundation for Research and Business, Seoul National University of Science and TechnologyInventors: Won Young Lee, Young Min Lee
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Patent number: 12362971Abstract: A receiver includes a decision feedback equalizer therein. The equalizer, which includes a cascaded arrangement of a first stage having a first plurality of summers therein and a second stage having a second plurality of summers therein, is configured to: (i) generate a compensated data signal by summing a current value of a data signal and a plurality of feedback signals, in response to a plurality of selection signals, (ii) generate a sampled signal including a decision value by sampling bits of the compensated data signal, in response to a plurality of divided strobe signals, and (iii) generate the feedback signals in response to a plurality of weights, the sampled signal, and at least one delayed version of the sampled signal.Type: GrantFiled: October 16, 2023Date of Patent: July 15, 2025Assignee: Samsung Electronics Co., Ltd.Inventor: Hyochang Kim
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Patent number: 12348342Abstract: According to one embodiment, a communication device includes first and second substrates. The first substrate includes an input circuit and a modulation circuit. The second substrate includes a receive circuit and an output circuit. The modulation circuit includes at least one delay circuit, outputs a modulated signal if an input signal has a first logic level, and using the at least one delay circuit, adjusts a length of a period to output the modulated signal shorter or longer than a period when the input signal has the first logic level. The receive circuit receives an electrical signal based on the modulated signal and demodulates the electrical signal. The output circuit outputs an output signal based on the electrical signal demodulated by the receive circuit.Type: GrantFiled: September 6, 2023Date of Patent: July 1, 2025Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Toyoaki Uo, Hiroaki Shimizu
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Patent number: 12335072Abstract: The present disclosure discloses a signal receiving apparatus having parameter optimization mechanism. A signal processing circuit processes a data signal according to at least one equalization parameter to generate an equalized data signal. A clock data recovery circuit performs clock data recovery on the equalized data signal according to a primary sampling signal and a primary threshold value to generate primary recovered data. A multi-sampling circuit performs clock data recovery on the equalized data signal according to secondary sampling signals and secondary threshold values to generate a plurality of pieces of secondary recovered data.Type: GrantFiled: December 19, 2023Date of Patent: June 17, 2025Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventor: Xiao-Guo Zheng
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Patent number: 12335362Abstract: A method for synchronizing a data frame and data symbols in a communication system includes generating a training sequence including a serial sequence of data symbols that are conjugate symmetric, inserting the training sequence in a transmitter-side data frame, converting constituent data symbols of the transmitter-side data frame to communication signals, transmitting the communication signals from a transmitter to a receiver, converting the communication signals to a stream of received data symbols, detecting presence of the training sequence in the stream of received data symbols, and identifying a position of a received data frame from the presence of the training sequence.Type: GrantFiled: June 12, 2023Date of Patent: June 17, 2025Assignee: Cable Television Laboratories, Inc.Inventors: Junwen Zhang, Mu Xu, Haipeng Zhang, Zhensheng Jia, Luis Alberto Campos
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Patent number: 12323155Abstract: A phase rotation control method includes: detecting whether a phase of an output clock signal of a phase interpolator is going to be switched from a current quadrant to a next quadrant according to a trigger signal to generate a state signal; determining a phase adjustment direction of the output clock signal according to an original phase control signal and the state signal to generate a update signal and first control signals; generating the trigger signal and a selection signal according to the update signal and generating second control signals according to the state signal and the first control signals; and when the phase of the output clock signal is switched to the next quadrant, outputting the second control signal as a phase control signal according to the selection signal, in which the phase interpolator adjusts the phase of the output clock signal according to the phase control signal.Type: GrantFiled: February 22, 2024Date of Patent: June 3, 2025Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Yao-Chia Liu, Tung-Hsien Tsai
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Patent number: 12315979Abstract: A device includes a transformer having primary windings and secondary windings, and a transmit circuit coupled to the primary windings. The transmit circuit is configured to receive an input signal, and provide a carrier signal to the primary windings responsive to the input signal. The device also includes a receive circuit coupled to the secondary windings. The receive circuit is configured to receive the carrier signal from the secondary windings, and provide an output signal responsive to the carrier signal. The receive circuit includes a variable capacitor coupled in parallel to the secondary windings, and a spread spectrum modulation circuit configured to modulate a capacitance of the variable capacitor.Type: GrantFiled: May 23, 2022Date of Patent: May 27, 2025Assignee: Texas Instruments IncorporatedInventors: Sreeram Subramanyam Nasum, Kashyap Barot
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Patent number: 12301389Abstract: Decision feedback equalization (DFE) taps and related apparatuses and methods are disclosed. An apparatus includes a first electrically controllable switch, a second electrically controllable switch, and one or more delay elements. The first electrically controllable switch receives a history bit and selectively provides the history bit to gate terminals of first transistors of a DFE tap circuitry. The second electrically controllable switch receives a complementary history bit and selectively provides the complementary history bit to second gate terminals of second transistors of the DFE tap circuitry. The one or more delay elements provide one or more delayed data integration clock signals responsive to one or more data integration clock signals. A complementary delayed data integration clock signal controls switching of the first electrically controllable switch and the second electrically controllable switch.Type: GrantFiled: January 19, 2024Date of Patent: May 13, 2025Assignee: Microchip Technology IncorporatedInventor: Ravish Soni
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Patent number: 12301696Abstract: A data transmitter includes a transmitting circuit configured to transmit data, the data including alternating odd-numbered data and even-numbered data. The transmitting circuit includes a first flip flop configured to receive the odd-numbered data and generate retimed odd-numbered data, and a second flip flop configured to receive the even-numbered data and generate retimed even-numbered data. The data transmitter includes a clock transmitting circuit configured to supply a clock signal to the transmitting circuit, the clock transmitting circuit including a clock driver configured to transmit the clock signal to a receiver that receives the data.Type: GrantFiled: February 2, 2023Date of Patent: May 13, 2025Assignee: Samsung Electronics Co., Ltd.Inventors: Byungsub Kim, Jaeyoung Seo
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Patent number: 12294399Abstract: Transceiver circuitry in an integrated circuit device includes a receive path including an analog front end for receiving analog signals from an analog transmission path and conditioning the analog signals, and an analog-to-digital converter configured to convert the conditioned analog signals into received digital signals for delivery to functional circuitry, and a transmit path including a digital front end configured to accept digital signals from the functional circuitry and to condition the accepted digital signals, and a digital-to-analog converter configured to convert the conditioned digital signals into analog signals for transmission onto the analog transmission path. At least one of the analog front end and the digital front end introduces distortion and outputs a distorted conditioned signal.Type: GrantFiled: January 4, 2024Date of Patent: May 6, 2025Assignee: Marvell Asia Pte LtdInventors: Ray Luan Nguyen, Benjamin Tomas Reyes, Geoffrey Hatcher, Stephen Jantzi
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Patent number: 12283143Abstract: A method of operating a seamless physical access control system comprises transferring communication session information using an out-of-band (OOB) communication channel of a smart ultra-wide band (UWB) capable device; establishing a secure OOB communication channel between the smart UWB capable device and a reader device using the communication session information; determining that a UWB enabled application of the smart UWB capable device needs secure ranging; establishing a secure UWB communication channel between the smart UWB capable device and the reader device; and transferring ranging information from a secure component of the smart UWB capable device to the reader device via the secure UWB communication channel.Type: GrantFiled: April 29, 2024Date of Patent: April 22, 2025Assignee: ASSA ABLOY ABInventors: Hans-Juergen Pirch, Jan Steffl, Sylvain Jacques Prevost, Fredrik Carl Stefan Einberg
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Patent number: 12273139Abstract: A method for estimating a performance of a wireless communication network for a given time-frequency resource allocation is disclosed. The communications in said wireless communication network are subject to interferences whose activation is modeled by a binary random variable bt indicating whether an interferer is active or not at a time instant t, the discrete-time stochastic process {bt}t?[??;+?] being modelled by a Markov chain with memory M. A frequency channel sequence associated with at least one set of consecutive observations of interference activation is determined from a frequency hopping sequence. The Markov chain associated with the determined frequency channel sequence is then identified and a set of probabilities of the identified Markov chain is updated according to the obtained at least one set of consecutive observations of interference activation.Type: GrantFiled: December 10, 2021Date of Patent: April 8, 2025Assignee: MITSUBISHI ELECTRIC CORPORATIONInventor: Nicolas Gresset
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Patent number: 12273964Abstract: This disclosure describes systems, methods, and devices related to multi-link operation. A device may configure a single N×N transmit (TX)/receive (RX) radio to a plurality of 1×1 TX/RX radios, where N is a positive integer. The device may monitor a first channel of a plurality of channels to determine its availability. The device may monitor a second channel of the plurality of channels to determine its availability. The device may identify a first control frame received from an access point (AP) multi-link device (MLD) on the second channel. The device may cause to send a second control frame to the AP MLD on the second channel. The device may configure back to a single N×N TX/RX radio to receive a data frame.Type: GrantFiled: March 13, 2023Date of Patent: April 8, 2025Assignee: Intel CorporationInventors: Minyoung Park, Po-Kai Huang, Thomas J. Kenney, Daniel Bravo, Ehud Reshef, Laurent Cariou, Dibakar Das, Dmitry Akhmetov
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Patent number: 12267122Abstract: A communication system includes a first physical-layer (PHY) transceiver and a second PHY transceiver. The first PHY transceiver includes (i) a first transmitter and (ii) a first receiver including a first equalizer. The second PHY transceiver includes (i) a second transmitter and (ii) a second receiver including a second equalizer. The first PHY transceiver and the second PHY transceiver are configured to communicate with one another over a full-duplex link, including training the first equalizer on a second training signal transmitted from the second PHY transceiver, and concurrently training the second equalizer on a first training signal transmitted from the first PHY transceiver.Type: GrantFiled: August 11, 2022Date of Patent: April 1, 2025Assignee: Marvell Asia Pte LtdInventors: Seid Alireza Razavi Majomard, Ehab Tahir, Ragnar Hlynur Jonsson
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Patent number: 12261723Abstract: Systems and methods relating to estimating data symbols encoded in a received signal that has been transmitted at a faster than Nyquist rate. The present invention uses a heuristic method for non-convex problems and involves an input matrix and received samples from the received signal. These are preconditioned and the preconditioned input matrix is factorized. The method then iterates a three-step process that estimates the sequence of data symbols based on the current estimate, the preconditioned input matrix, the preconditioned samples vector, a multiplier vector, and an auxiliary vector. The process then calculates the next multiplier vector and the next auxiliary vector. If the result indicates a minimum as compared to the best estimate, then the result is used as the best estimate. Multiple iterations of the process are performed, and the multiple iterations are repeated for multiple random initializations of the estimate.Type: GrantFiled: February 16, 2022Date of Patent: March 25, 2025Assignees: CARLETON UNIVERSITY, UNIVERSITY OF SASKATCHEWAN, SASKATOONInventors: Ahmed Mohamed Ali Ibrahim, Ebrahim Bedeer, Halim Yanikomeroglu