Abstract: Various embodiments relate to an end of packet (EOP) circuit, including: a reset pulse generator circuit configured to generate a reset pulse when a input signal transitions to a new value; an analog counter circuit configured to receive a squelch signal to start the counter and to receive the reset pulse to reset the counter; and an EOP detector circuit configured to produce a signal indicative that the input signal is an EOP signal based upon an output of the analog counter circuit.

Abstract: A microprocessor system comprises a first processing element, a second processing element, a point-to-point connection between the first processing element and the second processing element, and a communication bus connecting together at least the first processing element and the second processing element. The first processing element includes a first matrix computing unit and the second processing element includes a second matrix computing unit. The point-to-point connection is configured to provide at least a result of the first processing element to a data joiner component of the second processing element configured to join at least the provided result of the first processing element with a result of the second matrix computing unit.

Abstract: Methods and computing apparatuses for defending against model poisoning attacks in federated learning are described. One or more updates are obtained, where each update represents a respective difference between parameters (e.g. weights) of the global model and parameters (e.g. weights) of a respective local model. Random noise perturbation and normalization are applied to each update, to obtain one or more perturbed and normalized updates. The parameters (e.g. weights) of the global model are updated by adding an aggregation of the one or more perturbed and normalized updates to the parameters (e.g. weights) of the global model. In some examples, one or more learned parameters (e.g. weights) of the previous global model are also perturbed using random noise.

Abstract: An equalizing circuit includes a first current summer that receives a data signal and a first plurality of feedback signals, a first multiplexer that selects a first sampling clock signal from a plurality of clock signals using a signal that indicates a mode of operation of the equalizing circuit, and a first slicer that samples the output of the first current summer in accordance with timing provided by the first sampling clock signal. The equalizing circuit can have a second current summer that receives the data signal and a second plurality of feedback signals, a second multiplexer that selects a second sampling clock signal from the plurality of clock signals using the signal that indicates the mode of operation of the equalizing circuit, and a second slicer that samples the output of the second current summer according to timing provided by the second sampling clock signal.

Abstract: A system and method are described for distributed antenna wireless communications.

Abstract: Some embodiments of the present inventive concept provide a system for maintaining clock synchronization including an ultra-wideband (UWB) transmitting system and a UWB receiving system. The high precision input clock at the transmitting system produces a high precision clock frequency. A message is sent from the transmitting system including a transmit time of the message in UWB transmitter clock units. The message is received at the UWB receiving system at an arrival time in UWB receiver clock units. A time of flight (ToF) and an oscillator offset is calculated based on the transmit time included in the message and the arrival time. A tuning register uses the calculated oscillator adjustment to adjust the low precision resonator to synchronize the low precision resonator with the high precision input clock at the UWB transmitting system.

Abstract: A receiver included in a memory device includes a flag generator circuit, an equalizer circuit and an equalization controller circuit. The flag generator circuit is configured to, during a normal operation mode, generates a flag signal without an external command. The equalizer circuit is configured to, during the normal operation mode, receive an input data signal through a channel, generate an equalized signal by equalizing the input data signal based on an equalization coefficient, and generate a data sample signal including a plurality of data bits based on the equalized signal. The equalization controller circuit is configured to, during the normal operation mode, determine an amount of change in the equalization coefficient based on the flag signal, the equalized signal and the data sample signal, and perform a training operation in which the equalization coefficient is updated in real time based on the amount of change in the equalization coefficient.

Abstract: An adaptive serial general-purpose input output (ASGPIO) interface and a signal receiver thereof suitable for a secure control module (SCM) are provided. The ASGPIO interface includes a signal transmitter. The signal transmitter includes a first data buffer, a comparator, and an encoder. The first data buffer receives transmitted data and provides previously transmitted data. The comparator receives currently transmitted data and receives the previously transmitted data. In a first mode, the comparator compares the previously transmitted data with the currently transmitted data to generate a data variation information. The encoder, in the first mode, generates at least one index value and a corresponding instruction signal according to the data variation information. The signal transmitter sends the at least one index value as a serial signal and the instruction signal to a signal receiver.

Abstract: Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

Abstract: This disclosure describes systems, methods, and devices related to multi-link operation. A device may configure a single N×N transmit (TX)/receive (RX) radio to a plurality of 1×1 TX/RX radios, where N is a positive integer. The device may monitor a first channel of a plurality of channels to determine its availability. The device may monitor a second channel of the plurality of channels to determine its availability. The device may identify a first control frame received from an access point (AP) multi-link device (MLD) on the second channel. The device may cause to send a second control frame to the AP MLD on the second channel. The device may configure back to a single N×N TX/RX radio to receive a data frame.

Abstract: At high frequencies planned for 5G and 6G, phase noise may be a limiting factor on reliability and throughput. The default modulation scheme is currently QAM. Disclosed is a more versatile demodulation method based on the amplitude and phase of the sum-signal, which is the vector sum of the two branch amplitudes of QAM. The transmitter modulates a message by sum-signal amplitude and phase. The receiver can process the received waveform according to quadrature branches as usual, and determines the branch amplitudes. The receiver then calculates, from the branch amplitudes, the sum-signal amplitude and sum-signal phase for demodulation. The receiver can thereby obtain substantially enhanced phase-noise tolerance and amplitude spacing uniformity at virtually no cost. In addition, methods are disclosed for determining specific message fault types and non-square modulation tables depending on the type of mitigation required.

Abstract: The present technology relates to a communication apparatus and a communication method that permit realization of more reliable communication. Provided is a communication apparatus that includes a control section that performs control such that plural aggregated subframes are sent in a predetermined sequence for each frame included in each of spatially multiplexed streams when a frame is sent to another communication apparatus as plural spatially multiplexed streams. The present technology is applicable, for example, to a communication apparatus included in a wireless LAN system.

Abstract: A device includes a transmitter to transmit serialized data within a differential direct-current (DC) signal over a differential output line, a multiplexer circuit coupled to the transmitter, and a calibration circuit coupled between the differential output line, a multi-phase clock, and the multiplexer circuit. The multiplexer circuit is to select the serialized data from ones of multiple input lines according to a multi-phase clock and pass the selected serialized data to the transmitter. The serialized data includes a calibration bit pattern. The calibration circuit is to capture and digitize the differential DC signal into a digital stream, measure an error value from the digital stream that is associated with distortion based on the calibration bit pattern, convert the error value into a gradient value, and correct one or more phases of the multi-phase clock to compensate for the distortion based on the gradient value.

Abstract: An eye opening monitor device and an operation method thereof are provided. The eye opening monitor device includes a phase interpolator, a first sampling circuit, a second sampling circuit, and a clock centering circuit. The first sampling circuit samples a data signal according to a data clock to generate first sampled data. The second sampling circuit samples the data signal according to a phase interpolation clock to generate second sampled data. The phase interpolator changes a phase of the phase interpolation clock according to a phase interpolation code. The clock centering circuit counts multiple comparison results of the first sampled data and the second sampled data in multiple clock cycles to obtain an error count value for any one of different phase interpolation codes. The clock centering circuit determines the phase interpolation code provided to the phase interpolator based on the error count values corresponding to different phase interpolation codes.

Abstract: A communication apparatus determines, in a case where one or more other communication apparatuses are capable of performing coordinated communication by using a predetermined frequency band, whether or not performing high-speed connection with the one or more other communication apparatuses each operating as an access point is possible, and selects a Joint Transmission communication method on the basis that it is determined that it is possible to perform high-speed connection with the one or more other communication apparatuses each operating as an access point.

Abstract: An apparatus includes an estimation circuitry configured to receive a first set of one or more digital signals of transmitters of a communication system, and capture a set of one or more radio frequency signals that have been generated from the first set of digital signals The set of radio frequency signals being input of an antenna system of the communication system. Based on the first set of digital signals and the corresponding set of radio frequency signals, a set of weights related to a distortion effect caused by the generation of the radio frequency signals is derived. A received second set of digital signals is weighted using the set of weights, resulting in filtered signals. Using the filtered signals, a correction signal indicative of an interference caused by transmission of the second set of digital signals at a receiver of the communication system is estimated.

Abstract: Disclosed is an ultra-wideband (UWB) system and, more particularly, a UWB system using UWB ranging factor definition. The UWB system using the UWB ranging factor definition includes a memory in which a UWB ranging factor definition program is embedded and a processor which executes the program, wherein the program predefines UWB ranging factors to define a scrambled timestamp sequence (STS) index, an encryption key, and a nonce.

Abstract: A software defined radio type radio receiver is used in an environment that is self-sufficient in energy. The radio receiver has a receiving device, which receives the data in the form of a data packet or a portion thereof or a data stream at a certain data rate, and provides the data for further data processing. Wherein in an operating mode, the data is diverted at the receiving device and supplied to a microcontroller at a sampling rate which preferably can be defined. The microcontroller decimates the data by selecting a subset from the set of samples, and the microcontroller buffers in a memory and provides for further processing the decimated data.

Abstract: An operation method of a receiving device may comprise: receiving a periodic band-limited signal from a transmitting device; determining whether a carrier frequency of the periodic band-limited signal satisfies a constraint; converting the periodic band-limited signal into a digital high-frequency band signal by sampling the periodic band-limited signal at an extraction rate equal to or less than a Nyquist extraction rate when the carrier frequency satisfies the constraint; down-converting the digital high-frequency band signal into a digital baseband signal; rearranging samples of a plurality of periods of the digital baseband signal into one period; and generating a reconstructed signal by performing low-pass filtering with a bandwidth of the periodic band-limited signal on the digital baseband signal in which the samples are rearranged.

Abstract: Technologies directed to data transfer protocols for Ultra-Wideband (UWB) are described. One method includes a UWB radio of a first device receiving first data from an application. The first device sends data to second and third devices, the data identifying a number of data rounds, a duration of each round, a duration of a data slot, a duration of a data block, and a first slot index for the second device and a second slot index for the third device. The first device sends, during a first slot associated with the first slot index, the first data to the second device using the UWB radio. The first device sends, during a second slot associated with the second slot index, the first data to the third device using the UWB radio.