Abstract: Methods and apparatus for storing and retrieving data. In one implementation, a system includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least four memories, each having memory pages, data stored to at least two memories and retrieved from at least two memories in parallel, each buffer page having entries along a first dimension corresponding to the first order and entries along a second dimension corresponding to the second order, data stored in the first order and retrieved in the second order, at least one memory page stores data in multiple locations according to the first and second orders, two data elements consecutive in the first order stored in parallel to the memories, at least two data elements consecutive in the second order retrieved in parallel from the memories.

Abstract: A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A time allocator arbitrates the concurrent use of the graphics-rendering engine between each independent image being rendered.

Abstract: A graphics processor includes programmable arithmetic logic units (ALUs) for performing scalar arithmetic operations on pixel packets. For a selected scalar arithmetic operation, operands in pixel packets may be formatted in a S1.8 format to improve dynamic range. For at least one other scalar arithmetic operation, the pixel packets may be formatted in a different data format.

Abstract: A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.

Abstract: A memory management system provides microcode instructions that are divided into multiple tuned phases and stored as separate modules inside a phase code depository. A microcode manager, containing a mode detector, sequence identifier, code loader, drawing data processor and phase executor, interacts with a microcode processor and the phase code depository. The mode detector evaluates a user request for a desired mode. In response to a command from the mode detector, the sequence identifier selects a correct phase sequence that is needed to implement the desired mode. The code loader transfers the phase sequence from the phase code depository to the microcode processor where it is stored in a microcode instruction memory. The memory address for each module within the phase sequence is written to a microcode data memory.

Abstract: A graphics processor is disclosed having a programmable Arithmetic Logic Unit (ALU) stage for processing pixel packets. Scalar arithmetic operations are performed in the ALUs to implement a graphics function.

Abstract: Methods and apparatus for storing and retrieving data. In one implementation, a system includes: a data source, providing data in a first order; a data destination, receiving data in a second order; memory devices having memory pages, data stored in parallel and retrieved in parallel; each buffer page having entries along a first dimension corresponding to the first order and entries along a second dimension corresponding to the second order, data stored according to the first order using blocks of buffer pages, each block having a number of pages equal to a power of 2, data stored in the first order and retrieved in the second order, at least one memory page stores data in multiple locations according to the first and second orders, data elements consecutive in the first order are stored in parallel, data elements consecutive in the second order are retrieved in parallel.

Abstract: Method and apparatus for graphics processing is described. More particularly, a graphics processing subsystem capable of multi-pass graphics data processing is described. The graphics processing subsystem includes a geometry processor and a fragment processor, where output from the fragment processor is input compatible with the geometry processor. Data produced in a pass through a graphics data-processing pipeline including the fragment processor and geometry processor may be used as an input to processing during a subsequent pass. Data read from a texture map may be used to define or modify data, including vertex data, being processed in the geometry processor or the fragment processor.

Abstract: A central processing unit (CPU) configured to apply an intelligent wait methodology is provided. The CPU includes a chip select module that defines a chip select signal associated with an external device. The chip select module includes an address space configured to store addresses associated with the external device. The address space provides an address section. The address section is associated with the external device and is subdivided into address sub-sections associated with an address range and assigned through the chip select signal. The address sub-sections are configured to determine a bus cycle based on an association with either the CPU monitoring a wait line between the CPU and the external device or the CPU waiting for a number of wait states. A device and a method for optimizing a bus cycle length between a CPU and an external device in communication with the CPU are provided.

Abstract: An intelligent caching data structure and mechanisms for storing visual information via objects and data representing graphics information. The data structure is generally associated with mechanisms that intelligently control how the visual information therein is populated and used. The cache data structure can be traversed for direct rendering, or traversed for pre-processing the visual information into an instruction stream for another entity. Much of the data typically has no external reference to it, thereby enabling more of the information stored in the data structure to be processed to conserve resources. A transaction/batching-like model for updating the data structure enables external modifications to the data structure without interrupting reading from the data structure, and such that changes received are atomically implemented. A method and mechanism are provided to call back to an application program in order to create or re-create portions of the data structure as needed, to conserve resources.

Abstract: A page data processor capable of reducing a dead time or an output interrupting time of an output unit calculates an output start time in the output unit from a time necessary for rasterizing page data and a time necessary for outputting output data generated by the rasterization processing. The page data processor also generates a plurality of output files by dividing the output data every time the rasterized output data reaches a prescribed data size, and transmits the same to the output unit in units of the output files at the output start time. Thus, the page data processor can reduce the dead time of the output unit for improving the efficiency of printing/prepress steps.

Abstract: An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.

Abstract: A video routing system including a plurality of video routers VR(0), VR(1), . . . , VR(NR?1) coupled in a linear series. Each video router in the linear series may successively operate on a digital video stream. Each video router provides a synchronous clock along with its output video stream so a link interface buffer in the next video router can capture values from the output video stream in response to the synchronous clock. A common clock signal is distributed to each of the video routers. Each video router buffers the common clock signal to generate an output clock. The output clock is used as a read clock to read data out of the corresponding link interface buffer. The output clock is also used to generate the synchronous clock that is transmitted downstream.

Abstract: A method and mechanism for managing graphics data. A graphics unit is coupled to share a cache and a memory with a processor. The graphics unit is configured to partition rendered images into a plurality of subset areas. During the rendering of an image, data corresponding to subset areas of an image which require a relatively high number of accesses is deemed cacheable for a subsequent rendering. During a subsequent image rendering, if the graphics unit is required to evict data from a local buffer, the evicted data is only stored in the shared cache if a prior rendering indicated that the corresponding data is cacheable.

Abstract: Methods and apparatus for storing and retrieving data using two-dimensional arrays. In one implementation, a checkerboard buffer page system includes: a data source, providing data elements in a first order; a data destination, receiving data elements in a second order; memory devices each having memory pages, data elements stored in parallel to and retrieved in parallel from the memory devices; each buffer page having entries along a first dimension corresponding to the first order and entries along a second dimension corresponding to the second order, data elements stored in the first order and retrieved in the second order, at least one memory page stores data elements in multiple locations according to the first and second orders, at least two data elements consecutive in the first order stored in parallel, and where at least two data elements consecutive in the second order retrieved in parallel.

Abstract: A graphics system comprising a series of calculation units. The calculation units comprise a first subset and a second subset of calculation units. A first calculation unit of the series generates a first digital video stream and a second digital video stream. Each calculation unit of the first subset: (a) passes the second digital video stream to a next calculation unit of the series unmodified; and (b) computes first pixel values, injects or mixes the first pixel values into the first digital video stream, and passes the modified first digital video stream to the next calculation unit. Similarly, each calculation unit of the second subset injects or mixes second pixel values into the second digital video stream, and passes the first digital video stream unmodified. A last calculation unit of the series drives one or more display devices in response to the first and second digital video streams.

Abstract: Animation data is rendered in real time. Animated scenes include at least one texture-mapped surface (502). Each scene is rendered on demand, in immediate continuation from the last, and results of scene animation may be combined with image data from another real time image source. Textures (921) are pre-loaded into a texture memory (809) before a scene containing them is rendered. As a result of the necessity to perform rendering (1521) in real time, each frame has an available bandwidth (1501) for transferring a texture to the texture memory. Estimates of available bandwidth are generated (1302) by an adaptive statistical model. A texture required for transfer is split (1307) into portions (1801) that are transferred (1511) as a background operation, while real time rendering continues without loss of rendering quality.

Abstract: A graphics system comprising a scheduling network, a sample buffer and a plurality of filtering units. The sample buffer is configured to store sample generated by a rendering engine. The plurality of filtering units are coupled in a linear series. Each filtering unit of the linear series is configured to send a request for a scanline of sample bins to a first filtering unit of the linear series. The first filtering unit is configured to service the scanline requests by sending burst requests to a scheduling network and coordinating the flow of samples forming the bursts from the sample buffer to the filtering units.

Abstract: A graphics system configured with a scheduling network, a sample buffer, a rendering engine and a filtering engine. The rendering engine is configured to generate samples in response to received graphics data, and to forward the samples to the scheduling network for storage in the sample buffer. The filtering engine is configured to send a request for samples to the scheduling network. The scheduling network is configured to compare a video set designation of the request to a previous request designation, to update one or more state registers in one or more memory devices of the sample buffer in response to a determination that the video set designation of the request is different from the previous request designation, and to assert signals inducing a transfer of a collection of samples corresponding to the request from the one or more memory devices to the filtering engine.

Abstract: A data processing system has main memory and one or more caches. Data from main memory is cached while mitigating the effects of address pattern dependency. Main memory physical addresses are translated into main memory virtual address under the control of an operating system. The translation occurs on a page-by-page basis such that some of the virtual address bits are the same as some of the physical address bits. A portion of the address bits that are the same are selected and cache offset values are generated from the selected portion. Data is written to the cache at offset positions derived from the cache offset values.