Abstract: The present invention introduces circuitry and systems for performing two-dimensional motion compensation using a three-dimensional pipeline, as well as methods of operating the same. According to an exemplary embodiment, image processing circuitry is provided and includes both a two-dimensional image pipeline, which is operable to process two dimensional image data to generate successive two-dimensional image frames, and a three-dimensional image pipeline, which is operable to process three-dimensional image data to render successive three-dimensional image frames. The image processing circuitry further includes dual mode sub-processing circuitry, which is associated with each of the two- and three-dimensional image pipelines. The dual mode sub-processing circuitry is operable to perform motion compensation operations associated with the two-dimensional image pipeline in one mode and to perform rasterization operations associated the three-dimensional image pipeline in another mode.

Abstract: A novel storage format enabling a method for improved memory management of video images is described. The method includes receiving an image consisting of a plurality of color components. Once received, the plurality of color components is converted to a mixed format of planar format and packed format. The mixed packet format is implemented by storing one or more of the plurality of color components in a planar format and storing one or more of the plurality of color components in a packed format. A method for writing out video images is also described utilizing a write combining (WC) fame buffer. The decoding method motion compensates groups of macroblocks in order to eliminate partial writes from the WC frame buffer.

Abstract: Generally, graphics are displayed on a monitor or printed on an output device after a series of steps are performed, typically implemented in the form of a graphics pipeline, in the case of an object-oriented graphic image. Similarly, a digital picture or digital video image passes through a digital pipeline for the digital image or images to be displayed, printed, or otherwise processed. The present invention encompasses a system and method in which the stages of the graphics pipeline used to process a graphic object are interconnected to the stages of the digital pipeline used to process a bit-mapped image so that a single, interconnected pipeline can be used to process object-oriented graphic images, bit map images and/or images which contain graphics and bit map portions. This interconnected pipeline can be used to process images through various stages of the graphics pipeline followed by stages typically contained in the digital pipeline, or vice versa, to create desired effects.

Abstract: System and method for reserving a memory space for multithreaded processing is described. Memory space within a memory resource is allocated responsive to thread type. Examples of thread types for graphics processing include primitive, vertex and fragment types. Memory space allocated may be of a predetermined size for a thread type. Memory locations within a first memory space may be interleaved with memory locations within a second memory space.

Abstract: A method and system for synchronizing updates of vertex data by a processor with a graphics accelerator module that is fetching vertex data is disclosed. The method and system comprises providing vertex array range (VAR) and writing vertex data into the VAR. The method and system includes providing a command into a command stream of the graphics accelerator module indicating that the vertex data has written into the VAR, and providing a fence condition based upon the command. A system and method in accordance with the present invention thus permits extremely high vertex processing rates via vertex arrays or vertex buffers even when the processor lacks the necessary data movement bandwidth. By passing indices in lieu of the vertex data, the processor is capable of keeping up with the rate at which a vertex engine of the graphics accelerator module can consume vertices.

Abstract: A data format employing multiple different headers associated with corresponding OSD content facilitates the implementation of an efficient and flexible OSD management and control system. Each header contains a unique display characteristic or set of display characteristics for the interpretation and presentation of an associated OSD pixel map. In using this system, the presentation or modification of an OSD involves the selection of the header, associated with the OSD, having the desired display characteristics to be used in presenting or modifying the OSD.

Abstract: A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A time allocator arbitrates the concurrent use of the graphics-rendering engine between each independent image being rendered.

Abstract: A method and apparatus for supporting anti-aliasing oversampling in a video graphics system that utilizes a custom memory for storage of the frame buffer is presented. The custom memory includes a memory array that stores the frame buffer as well as a data path that performs at least a portion of the blending operations associated with pixel fragments generated by a graphics processor. The fragments produced by a graphics processor are oversampled fragments such that each fragment may include a plurality of samples. If the sample set for a particular pixel location can be compressed, the compressed sample set is stored within the frame buffer of the custom memory circuit. However, if such compression is not possible, pointer information is stored within the frame buffer on the custom memory, and a sample memory controller included on the graphics processor maintains a complete sample set for the pixel location within a sample memory.

Abstract: A system, method, and article of manufacture are provided for allowing direct memory access to graphics vertex data by a graphics accelerator module. First, vertex data is stored in memory. Next, an index is received which is representative of a portion of the vertex data in the memory. A location is then determined in the memory in which the portion of the vertex data is stored. Such portion of the vertex data may thereafter be directly retrieved from the determined location in the memory while bypassing a processor.

Abstract: A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.

Abstract: An electronic device that has an integrated central processing unit (CPU) including a pre-fetch stride analyzer and an out-of-order engine is provided. The electronic device also has a graphics engine, having graphics memory, that is coupled to the integrated CPU. A main memory that is coupled to a memory controller is provided. The memory controller is also coupled to the CPU and the graphics engine. The device has a host address decoder coupled to the integrated CPU. A front side bus (FSB) is provided that is coupled to the integrated CPU and the host address decoder. Also provided is a plurality of memory components. Accordingly, either the plurality of memory components or the graphics memory can be shared to perform alternate memory functions. Additionally, a method is provided that determines allocation availability between memory components in an integrated computer processing unit.

Abstract: A method and a device of consistency buffer for a high performance 3D graphic accelerator is disclosed to retain consistency without detecting any overlapping region in advance but determining an overlapping with respect to a rendered pixel.

Abstract: A synchronized two-level cache including a Level 1 cache and a Level 2 cache is implemented in a graphics processing system. The Level 2 cache is further partitioned into a number of slots which are dynamically allocated to texture maps as needed. The reference counter of each of the cache lines in each cache level is tracked so that a cache line is not overwritten with new data prior to transferring old data out to the recipient device. The age status of each cache line is tracked so that the oldest cache line is overwritten first. The use of synchronized two-level cache system conserves system memory bandwidth and reduces memory latency, thereby improving the graphics processing system's performance.

Abstract: A video routing system including video routers VR(0), VR(1), . . . , VR(NR−1) coupled in a linear series. Each video router in the linear series successively operates on a digital video stream. Each video router provides a synchronous clock with its output video stream so a link interface buffer in the next video router can capture values from the output video stream in response to the synchronous clock. Each video router buffers a common clock to generate a local output clock. The output clock is used as a read clock to read data out of the corresponding link interface buffer. The output clock is also used to generate the synchronous clock that is transmitted downstream. To initialize the series, reset is sequentially removed from each video router starting from the first video router after the common clock has stabilized.

Abstract: A controller (or controller chip) providing reduced power consumption without impacting performance is disclosed. The controller monitors activity of components within the controller which require access to a local memory, and then decreases a clocking frequency for a memory interface to the local memory when the monitoring indicates that reduced amounts of activity are present. Following such a decrease in the clocking frequency, when increased amounts of activity are detected, the clocking frequency is increased for high performance operation. The controller thus tailors the clocking frequency for the memory interface in accordance with the amount of activity of these components that require access to the local memory so that overall less power is used by the controller yet the performance is essentially not hindered. In one embodiment, the controller is a graphics controller, as such controllers require access to local memories.

Abstract: A method for enabling reduced transport display in a computer image generator connected to a host simulator which receives real-time input. The first step is performing real-time matrices calculations with the real-time input. The next step is processing geometry for primitives in a scene and storing the primitives in a double-buffered geometry buffer. The geometry buffer toggles as soon as the geometry processing is done without waiting for a field sync signal which reduces the transport delay normally found in image generation systems. Another step is rendering the primitives into a pixel frame buffer as soon as the geometry buffer toggles. The final step is displaying the pixel frame buffer. The rendering hardware and geometry processing hardware can also include enough processing power to complete the geometric transformations and rendering and in less than one display frame.

Abstract: A graphics subsystem including a RAMDAC for connection to a graphics bus implemented on an integrated circuit chip separate from a graphics processor. In one embodiment, the graphics processor is configured to render digital image information in response to graphics commands and to store the digital image information in a memory. The RAMDAC IC includes a conversion unit, which includes a color mapping unit and a digital-to-analog converter and is configured to convert a representation of the digital image information into one or more analog signals for driving a video display. The graphics subsystem further includes a Direct Memory Access (DMA) controller implemented on the second integrated circuit chip. The DMA controller is configured to generate read requests to retrieve the digital image information stored in the memory to thereby cause the digital image information to be provided to the conversion unit.

Abstract: A method for rendering graphics on a server. In a preferred embodiment, a server receives a request from a requesting device for graphics. The server determines the fastest available rendering resource and dispatches the request to this fastest available rendering resource. Once the graphics have been rendered, the server sends the graphics to the requesting device for presentation to a user.

Abstract: A method and system for utilizing processor(s) and bypass processor(s) of a computer graphics system are disclosed. The processor(s) and bypass processor(s) render primitives, which are ordered based on their left corners. The method and system include providing a merge circuit, a distributor, a feedback circuit and a controller. The merge circuit determines left and right edges for each primitive. The distributor is coupled with feedback circuit and outputs a first portion of the primitives. The distributor provides a second portion of the primitives to the processor(s) and a third portion of the primitives to the bypass processor(s) if the first portion includes more primitives than there are processor(s). The second portion includes no more primitives than there are processor(s). The feedback circuit, coupled to the merge circuit, re-inputs a fourth portion of the primitives to the bypass processor(s) until the first portion has been rendered for a line.

Abstract: A method, apparatus and article of manufacture are provided for sequencing graphics processing in a transform or lighting operation. A plurality of mode bits are first received which are indicative of the status of a plurality of modes of process operations. A plurality of addresses are then identified in memory based on the mode bits. Such addresses are then accessed in the memory for retrieving code segments which each are adapted to carry out the process operations in accordance with the status of the modes. The code segments are subsequently executed within a transform or lighting module for processing vertex data.