Abstract: Displaying video images includes determining which of at least two video field polarities a video display is in a state to display and choosing a stored video field for display based on the determined state.

Abstract: A scaleable network based computer system having a distributed texture memory architecture. A network residing within the computer system is used to transmit packets between a host processor and a number of subsystems. Three basic types of subsystems are coupled to the network: a geometry subsystem is used to process primitives; a rasterization subsystem is used to render pixels; and a display subsystem is used to drive a computer monitor. Any number and combination of these three types of subsystems can be coupled to one or more network chips to implement a wide variety of configurations. One or more memory chips can be coupled to any of the rasterization subsystems. These memory chips are used to store texture data. A rasterization subsystem can access texture data from its associated memory chips or can request texture data residing within any of the other memory chips.

Abstract: A graphics processing system has a cache which is partitionable into two or more slots. Once partitioned, the slots are dynamically allocatable to one or more texture maps. First, number of texture maps needed to render a given scene is determined. Then, available slots of the cache are allocated to the texture maps. Sometimes, more slots are allocated to the largest texture map. At other times, more slots are allocated to the texture map which is likely to be used most often. The slots can also be allocated equally to all of the texture maps needed.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port (“AGP”) bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table (“GART table”) is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page.

Abstract: A method and system for efficient buffer rendering. An object mask, typically a character font mask, is aligned with a memory tiling arrangement (1102). A tile map is generated (1104) to indicate active tiles. An active tile is selected (1106) and the portion of the buffer corresponding to the active tile is transferred (1108) from a first memory, typically an off-chip memory, to a second memory, typically an on-chip memory to allow a processor to render the band buffer tile. The portion of the band buffer is rendered (1110) and returned (1112) to the first memory. The next active tile is selected and the process continues until all active tiles have been rendered (1114).

Abstract: An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.

Abstract: A memory controller hub has a data stream controller adapted to use a system memory to store graphics data and to control functions of the system memory, a processor interface, a system memory interface, a graphics subsystem coupled to the data stream controller and adapted to perform graphics operations on graphics data, and a graphics port adapted to couple the memory controller hub to an external graphics device.

Abstract: A method and apparatus in a graphics system. The graphics system includes an input, wherein the input receives graphics data, wherein the graphics data includes position coordinates and a depth coordinate for an object. An output is present in which the output transmits processed graphics data. The graphics system also contains a plurality of processing elements, wherein the plurality of processing elements generates the processed graphics data. A first processing element within the plurality of processing elements is connected to the input and a last processing element within the plurality of processing elements is connected to the output. A selected processing element within the plurality of processing element receives the position coordinates and the depth coordinate, inverts the depth coordinate to form an inverted depth coordinate, and multiplies the position coordinates by the inverted depth coordinate.

Abstract: In a 3D interactive computer graphics system such as a video game display system, polygon vertex data is fed to a 3D graphics processor/display engine via a vertex cache used to cache and organize indexed primitive vertex data streams. The vertex cache may be a small, low-latency cache memory local to the display engine hardware. Polygons can be represented as indexed arrays, e.g., indexed linear lists of data components representing some feature of a vertex (for example, positions, colors, surface normals, or texture coordinates). The vertex cache can fetch the relevant blocks of indexed vertex attribute data on an as-needed basis to make it available to the display processor—providing spatial locality for display processing without requiring the vertex data to be prestored in display order.

Abstract: A graphics geometry cache. The basic idea of one embodiment in accordance with the present invention is to utilize a graphics geometry cache together with a graphics pipeline. The graphics geometry cache is a relatively small cache (e.g., 128 entries) used for storing and maintaining vertex data. Specifically, the results of computations performed on vertices by the graphics pipeline (e.g., transformed vertices and attributes such as color) are cached within the graphics geometry cache. Furthermore, the cached entries are tagged by their corresponding vertex coordinates. Subsequently, when a particular vertex is specified for the graphics pipeline, a tag compare is executed through a hashing function to determine whether the graphics geometry data for that particular vertex is stored within the graphics geometry cache.

Abstract: A system and method are provided for optimizing the translation of virtual addresses into physical addresses for a graphics address remapping table (GART). In the system and method, a translation look-aside buffer cache has a plurality of translation look-aside buffer entries. Each translation look-aside buffer entry is operable to buffer information which may be accessed for use in translating a virtual address into a physical address. A least recently used pointer circuit is operable to point to a translation look-aside buffer entry buffering information least recently used in the translation look-aside buffer cache. During operation, updates to the least recently used pointer circuit may be pipelined with corresponding accesses to the translation look-aside buffer cache.

Abstract: The present invention is characterized by first performing the necessary rendering in the frame period, then during the remaining time of that frame period, rewriting the texture data in the texture buffer memory. The image rendering process for each frame is performed first, then after the rendering process has been completed for the frame, if there is remaining time, that time is used to rewrite the texture data. Therefore, the rendering process is not interrupted, the displayed image is not interrupted or frozen, and it is possible to rewrite the texture data in the small-capacity texture buffer memory and make it possible to use virtually a lot of texture data to render one scene.

Abstract: Methods and systems for optimizing graphics data processing employ various binning flush algorithms to optimize the utilization of binning memory in a graphics system. Binning flush algorithms provide for processing all geometry and commands binned up to the point the binning memory becomes unavailable, and storing and restoring all necessary intermediate data generated during the partial tile rendering.

Abstract: A method and apparatus for generation of pixel lookahead information in a cached computer graphics system is provided. For each pixel-based memory operation, several data items may be generated, such as numerical values representing a coordinate point in an image coordinate space or display coordinate space and characteristic data representing a color value or depth value for the pixel. In addition, lookahead data correlated with the coordinate data is generated. The pixel operation is then issued with the characteristic data, the coordinate data, and the lookahead data. The lookahead data may contain a lookahead vector, which specifies a lookahead vector direction and a lookahead vector length, and a lookahead valid flag, which indicates whether associated lookahead data is valid for the pixel operation.

Abstract: A method, apparatus and article of manufacture are provided for sequencing graphics processing in a transform or lighting operation. A plurality of mode bits are first received which are indicative of the status of a plurality of modes of process operations. A plurality of addresses are then identified in memory based on the mode bits. Such addresses are then accessed in the memory for retrieving code segments which each are adapted to carry out the process operations in accordance with the status of the modes. The code segments are subsequently executed within a transform or lighting module for processing vertex data.

Abstract: A method, apparatus and article of manufacture are provided for sequencing graphics processing in a transform or lighting operation. A plurality of mode bits are first received which are indicative of the status of a plurality of modes of process operations. A plurality of addresses are then identified in memory based on the mode bits. Such addresses are then accessed in the memory for retrieving code segments which each are adapted to carry out the process operations in accordance with the status of the modes. The code segments are subsequently executed within a transform or lighting module for processing vertex data.

Abstract: A method, apparatus and article of manufacture are provided for managing vertex data in a vertex buffer. First, vertex data is received and stored in the vertex buffer. Thereafter, the vertex data is outputted from the vertex buffer to a processing module. During operation, a plurality of command bits is passed from the vertex buffer for determining a manner in which the vertex data is inputted and processed in the input buffer of the processing module. Such command bits are received from a command bit source. Further, a plurality of mode bits indicative of a status of a plurality of modes of process operations is passed. Such mode bits are received from a mode bit source. The mode bits are adapted for determining a manner in which the vertex data is processed in the processing module.

Abstract: In a computer system, main memory is accessed via a cache. Locations in a main memory are accessed by a process with reference to addresses. Each address comprises virtual bits and physical address bits. Selected bits of the physical address bits identify areas in the cache. Permutations of the selected bits are used to identify buffer alignments in main memory, in response to an identification of requirements for the process.