Abstract: A semiconductor memory device includes a memory cell including a floating body region and storing data on the basis of the amount of charges in the floating body region; word lines; a counter cell array including counter cells provided to correspond to the word lines, the counter cell array storing the number of times of activation of the word lines; an adder incrementing the number of times of activation, the number of times of activation being read from the counter cell array; a counter buffer circuit temporarily storing the number of times of activation and writing back the incremented number of times of activation to the counter cell array; and a refresh request circuit outputting an instruction to execute a refresh operation to the memory cells connected to the word line when the number of times of activation reaches a predetermined value.

Abstract: A semiconductor wafer includes a plurality of semiconductor chip regions including ferroelectric memory devices, a test chip region, and a wiring that connects each of the plurality of semiconductor chip regions with the test chip region.

Abstract: A semiconductor integrated circuit device includes a plurality of sense amplifier line pairs, a plurality of sense amplifier latch circuits respectively connected to the sense amplifier line pairs, and a sense amplifier driver circuit which supplies a sense amplifier activation signal to the sense amplifier latch circuits. The sense amplifier driver circuit is provided for each of the plurality of sense amplifier latch circuits and supplies the sense amplifier activation signal to each of the plurality of sense amplifier latch circuits.

Abstract: A memory device includes a plurality of memory cells and a comparison circuit that compares a set of selected memory cells with at least one reference cell having a threshold voltage. The comparison circuit includes a bias circuit that applies a biasing voltage having a substantially monotone time pattern to the selected memory cells and to the at least one reference cell, sense amplifiers that detect the reaching of a comparison current by a cell current of each selected memory cell and by a reference current of each reference cell, a logic unit that determines a condition of each selected memory cell according to a temporal relation of the reaching of the comparison current by the corresponding cell current and by the at least one reference current, and a time shift structure that time shifts at least one of said detections according to at least one predefined interval to emulate the comparison with at least one further reference cell having a further threshold voltage.

Abstract: A method, device, and system are disclosed. In one embodiment, the device comprises an array of flash memory blocks to store information in a multiple bit per cell mode, one or more flash memory blocks external to the array to store information in a single bit per cell mode, and a memory controller capable of allowing access to the array and the one or more flash memory blocks external to the array.

Abstract: Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.

Abstract: A circuit and method for producing a read clock signal in a semiconductor memory device from an input clock signal to ensure that the read access time does not exceed the clock cycle time. One of a plurality of delay amounts is selected to be imposed on the input clock signal depending on the frequency of the clock signal.

Abstract: A data transmission system, particularly as part of a DDR-III memory chip communication circuit, performs a data transmission operation without preamble. The data transmission system includes at least one data line with an on die termination that can be turned on and turned off, and the chip end of the data line is connected to a positive or to a less positive, grounded, or negative supply voltage line by a pull-up or pull-down resistor. Alternatively, a data transmission system is operated with a timing by which the termination circuits to be turned on for respective operating state are not turned on until the drivers to be activated for the respective operating state have been activated.

Abstract: The power required to search a content addressable memory (CAM) is substantially reduced by forming the CAM to have a number of CAM banks with a corresponding number of power switches that control power to the CAM banks, and then controlling the power to search the CAM banks one at a time.

Abstract: A method and apparatus for filtering failures due to must-repair rows or columns from a memory test fail summary image includes current available redundant row failure counts respectively associated with rows of a memory device and current available redundant column failure counts associated with columns of the device. Respective failure counts are preloaded with the respective values of redundant rows and columns available for repairing the device. When failures in memory cells of the device are encountered, either during test, or during scan of an earlier generated error image, the row and column failure counts associated with the rows and columns containing the memory cell failures are decremented. At the end of a test, the value of the failure counts indicates whether the corresponding row or column contain any failures at all, whether the corresponding row or column is designated as a “must-repair” row or column, and otherwise how many errors the corresponding row or column contain.

Abstract: An advanced multi-bit magnetic random access memory device and a method for writing to the advanced multi-bit magnetic random access memory device. The magnetic memory includes one or more pair-cells. A pair-cell is two memory cells. Each memory cell has a magnetic multilayer structure. The structure includes a magnetically changeable ferromagnetic layer, a ferromagnetic reference layer having a non-changeable magnetization state, and a corresponding spacer layer separating the ferromagnetic layers. The memory cells are arranged such that an effective remnant magnetization of each of the cells is non-parallel from the cells' long-axis. This allows for more than one-bit to be stored as well as for efficient writing and reduced power consumption.

Abstract: A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register.

Abstract: An electronic device includes a memory cell that utilizes a bi-directional low impedance, low voltage drop full pass gate to connect a bit cell to a bit write line during a write phase, and during a read phase the full pass gate can remain off and a high input impedance read port can acquire and transmit the logic state stored by the memory cell to another subsystem. The full pass gate can be implemented by connecting a P type metal semiconductor field effect transistor (PMOS) in parallel with an NMOS device and driving the gates of the transistors with a differential signal. When a write operation requires a current to flow in a first direction, the PMOS device provides a negligible voltage drop, and when the write operation requires current to flow in a second or the opposite direction, the NMOS device can provide a negligible voltage.

Abstract: A non-volatile semiconductor memory device including a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, and a sense amplifier circuit for reading said memory cell array, wherein the sense amplifier circuit includes: a first transistor disposed between a bit line of the memory cell array and a sense node to serve for sensing bit line data, the first transistor being driven by a voltage generating circuit including a boost circuit to transfer a bit line voltage determined in response to data of a selected memory cell to the sense node; a second transistor coupled to the sense node for precharging the sense node prior to bit line data sensing; a data latch for judging a transferred bit line voltage level to store a sensed data therein; and a capacitor for boosting the sense node, one end thereof being connected to the sense node, the other end thereof being selectively driven by a boost-use voltage.

Abstract: A method of testing a programmable resistance memory element. The method includes applying a plurality of reset pulses to the memory element. Each of the reset pulses having an energy which is greater than the minimum energy needed to program the memory element from its set state to its reset state.

Abstract: A semiconductor memory device is provided that uses a single wordline to access both storage cells of a so-called twin cell. A memory device comprises a plurality of wordlines and a plurality of bitlines in an array, with a plurality of storage cells at certain intersections of wordlines and bitlines. A plurality of sense amplifiers are provided, each of which is connected to at least a first pair of bitlines to detect a voltage difference on the bitlines caused by the charge from a twin storage cell comprised of first and second storage cells at the intersection of a single wordline with said first pair of bitlines, respectively. As a result, each cell of a twin storage cell can be accessed with a single wordline.

Abstract: A core-based multi-bit memory (400) having a dual-bit dynamic referencing architecture (408, 410) fabricated on the memory core (401). A first reference array (408) and a second reference array (410) are fabricated on the memory core (401) such that a reference cell pair (185) comprising one cell (182) of the first reference array (408) and a corresponding cell (184) of the second reference array (410) are read and averaged to provide a reference voltage for reading a data array(s).

Abstract: The present invention relates to a memory cell arrangement comprising a multiplicity of DRAM memory cells which are arranged in cell rows and cell columns and the selection transistor of which comprises in each case a first gate electrode and also a rear side electrode. The memory cell arrangement contains word lines and also rear side electrode lines which are arranged in each case alternately between adjacent cell columns. The invention provides for in each case the first gate electrodes of adjacent cell columns to be connected to the word line lying between the cell columns and in each case the rear side electrodes of adjacent cell columns to be connected to the rear side line lying between the cell columns. All the rear side lines are held at a constant potential, while for reading from a memory cell that word line is addressed to which the first gate electrode of the memory cell to be read is connected.

Abstract: A non-volatile content addressable memory cell comprises: a first phase change material element, the first phase change material element having one end connected to a match-line; a first transistor, the first transistor having a gate connected to a word-line, a source connected to a true bit-read-write-search-line, and a drain connected to another end of the first phase change material element; a second phase change material element, the second phase change material element having one end connected to the match-line; and a second transistor, the second transistor having a gate connected to the word-line, a source connected to a complementary bit-read-write-search-line, and a drain connected to another end of the second phase change material element.

Abstract: An overdrive period control device includes a pre-charge circuit connected to a node on which a potential is detected and for raising a potential at the node to a first potential; a delay element one terminal of which is connected to the node; a charge circuit supplying a power source voltage to the other terminal of the delay element at the input timing of a signal from the outside and raising the potential at the node to the power source voltage; and a comparison circuit comparing the potential at the node with a reference potential and detecting the timing at which both levels of the potentials coincide. The device outputs a signal indicating a period determined by the input timing of the signal from the outside and the timing in which the comparison circuit detects that the levels coincide.