Patents Examined by Dang Nguyen
  • Program method of flash memory device
    Patent number: 8174894
    Abstract: A program method of a flash memory device includes inputting a first data and a second data to a page buffer coupled to memory cells including an even page and an odd page, pre-programming a first memory cell of the odd page using the first data, programming a second memory cell of the even page using the second data, and programming the pre-programmed first memory cell using the first data.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: May 8, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ju In Kim
  • Semiconductor integrated circuit device
    Patent number: 8174901
    Abstract: This invention is to reduce the number of memory gate drivers, while lessening the number of times of disturb occurrence in a memory array configuration that implements writing in small byte units. A memory array comprises a plurality of sub-arrays, MG transfers, SL drivers, and CG drivers. Each sub-array includes a plurality of memory gate lines, control gate lines, source lines, and bit lines. Memory cells are arranged in positions of intersections of these lines. The control gate lines, CG drivers, source lines, and SL drivers are common to the sub-arrays, whereas the memory gate lines and MG buffer circuits are provided for each sub-array. Thereby, the units in which data is written are decreased and adverse effects of disturb are reduced without increasing the circuit size of the memory array.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: May 8, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Ken Matsubara, Hideo Kasai, Kenji Kawada, Makoto Mizuno
  • Bit line precharge circuit and a semiconductor memory apparatus using the same
    Patent number: 8174916
    Abstract: A bit line precharge circuit includes a precharge signal generation unit configured to generate first and second precharge signals that are enabled at different timing points by receiving a bit line equalizing signal; a first precharge unit configured to connect a pair of bit lines to each other in response to the first precharge signal and supply a bit line precharge voltage to the pair of bit lines; and a second precharge unit configured to supply the bit line precharge voltage to the bit line in response to the second precharge signal.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: May 8, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyung Sik Won
  • Semiconductor memory apparatus
    Patent number: 8164962
    Abstract: A semiconductor memory apparatus includes an SRAM circuit having first SRAM cells that store data and second SRAM cells that amplify a potential difference of the data and store the potential difference, a word line driver circuit that outputs a first control signal for selecting one of the first SRAM cells to be read/written the data and a second control signal for selecting one of the second SRAM cells to be read/written the potential difference, a sense amplifier circuit that amplifies a potential difference of a read signal output from a bit line pair of the second SRAM cell selected according to the second control signal, and a write driver circuit that outputs a write signal to the bit line pair of the second SRAM cell selected according to the second control signal, and the write signal has a potential difference between bit lines larger than the read signal.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: April 24, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Koichi Takeda
  • Electronic device with a programmable resistive element and a method for blocking a device
    Patent number: 8159857
    Abstract: One or more embodiments relate to an electronic device comprising a circuitry and a programmable resistive element. The programmable resistive element comprises a first and a second state, wherein the programmable resistive element is configured to allow switching from the second state into the first state in response to a signal comprising at least a predefined level. The circuitry is configured to provide signals up the predefined level, wherein the circuitry is configured to provide a switch signal to the programmable resistive element, wherein the switch signal causes switching from the first into the second state.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: April 17, 2012
    Assignee: Infineon Technologies AG
    Inventors: Berndt Gammel, Thomas Nirschl, Gerd Dirscherl, Philip Schlazer
  • Two levels of voltage regulation supplied for logic and data programming voltage of a memory device
    Patent number: 8159897
    Abstract: Systems and methods involve the use of a flash memory device having multiple flash memory cells. A first interface is adapted to receive power for selectively programming each flash memory cell. A second interface is adapted to receive power supplied to logic level circuitry to perform the selection of flash memory cells to be supplied with power from the first input during a write operation.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: April 17, 2012
    Assignee: Apple Inc.
    Inventors: Michael J. Cornwell, Christopher P. Dudte
  • Semiconductor memory device
    Patent number: 8159852
    Abstract: A semiconductor memory device includes first and second driving transistors; first and second load transistors; and first and second transmission transistors. Their respective drain diffusion layers of the transistors are isolated from one another. The semiconductor memory device also includes a bit cell in which the first and second driving transistors, the first and second load transistors, and the first and second transmission transistors are arranged; a first wiring for connecting their respective drains of the first driving transistor, the first load transistor, and the first transmission transistor; and a second wiring for connecting their respective drains of the second driving transistor, the second load transistor, and the second transmission transistor.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: April 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Kouchi, Yutaka Tanaka
  • Circuits, devices, systems, and methods of operation for capturing data signals
    Patent number: 8154931
    Abstract: Embodiments of the invention are described for driving data onto a data bus. The embodiments include a data driver circuit having a data capture circuit coupled to the data bus. The data capture circuit receives a data signal relative to a write strobe signal and captures a first data digit of the data signal responsive to a first edge of the write strobe signal and at least a second data digit responsive to a second edge of the write strobe signal. The data driver circuit includes a feedback capture circuit that captures each of the data digits of the data signal in substantially the same manner as the data capture circuit, and also generates a latch control signal indicative of when each data bits is latched. The latch control signal is provided to a write control circuit coupled to the feedback capture circuit and the data capture circuit.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: April 10, 2012
    Assignee: Micron Technology, Inc.
    Inventor: James Brian Johnson
  • Semiconductor integrated circuit
    Patent number: 8154943
    Abstract: A semiconductor integrated circuit includes a first region configured to operate at a specified first voltage, a second region configured to operate at a varying second voltage, and a memory device formed between the first region and the second region so as to straddle the first and second regions, wherein the memory device comprises a first port driven at the first voltage to transmit an output signal to and receive an input signal from the first region, a second port driven at the second voltage to transmit an output signal to and receive an input signal from the second region, and a memory cell accessed by the first and second ports.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: April 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yukihiro Fujimoto
  • Low power memory architecture
    Patent number: 8149634
    Abstract: A memory architecture and circuits for minimizing current leakage in the memory array. Subdivisions of the memory array each have local power grids that can be selectively connected to power supplies, such that only an accessed subdivision will receive power to execute the memory access operation. The memory array can further include databuses which are precharged to one voltage during idle times and a second voltage during active read cycles, which reduces leakage current in datapath circuitry connected to the databuses within the memory array blocks.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: April 3, 2012
    Assignee: Mosaid Technologies Incorporated
    Inventor: Valerie L. Lines
  • Multi-level phase change random access memory device
    Patent number: 8149608
    Abstract: A multi-level phase change random access memory device includes a first electrode, a second electrode, and a phase change material disposed between the first electrode and the second electrode. The multi-level phase change random access memory device also includes a variable bias source coupled to the first electrode. The variable bias source provides a respective bias applied at the first electrode to form a portion of the phase change material to have one of an amorphous state and different crystal states for storing multi-bits data.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: April 3, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Tae-Yon Lee
  • Cross-point memory devices, electronic systems including cross-point memory devices and methods of accessing a plurality of memory cells in a cross-point memory array
    Patent number: 8144506
    Abstract: Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: March 27, 2012
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Jun Liu
  • Nonvolatile semiconductor storage device
    Patent number: 8139388
    Abstract: This invention has the purpose of providing a nonvolatile semiconductor storage device which is capable of entering multivalued storage in a FeFET unit without requiring preparation of a plurality of voltage sources. The nonvolatile semiconductor storage device is provided with multivalued ferroelectric memory cells which impart varied quantities of polarization to a ferroelectric material by applying pulse voltages having one and the same height and varied widths and consequently produce varied states of storage in conformity with the varied quantities of polarization.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: March 20, 2012
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Mitsue Takahashi, Shigeki Sakai, Shouyu Wang, Ken Takeuchi
  • Method of erasing a memory device including complementary nonvolatile memory devices
    Patent number: 8139387
    Abstract: Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: March 20, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-dong Park, Jo-won Lee, Chung-woo Kim, Eun-hong Lee, Sun-ae Seo, Woo-joo Kim, Hee-soon Chae, Soo-doo Chae, I-hun Song
  • Mixed data rates in memory devices and systems
    Patent number: 8139390
    Abstract: Mixed data rates in a memory system is disclosed. The system includes at least one semiconductor memory device and another device defining a ring topology. The semiconductor memory device includes input circuitry for receiving a clock signal having a frequency at least substantially equal to a frequency x. A first set of circuit elements are each clocked by a same or respective first internal signal having a frequency at least substantially equal to the frequency x. A second set of circuit elements are each clocked by a same or a respective second internal signal having a frequency at least substantially double that of the frequency x.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: March 20, 2012
    Assignee: MOSAID Technologies Incorporated
    Inventor: HakJune Oh
  • Scalable electrically eraseable and programmable memory
    Patent number: 8139408
    Abstract: A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a third source region continuous with source regions of other non-volatile memory transistors located in the same row as the EEPROM cell pair.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: March 20, 2012
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Sorin S. Georgescu, Peter Cosmin, George Smarandoiu
  • Memory device biasing method and apparatus
    Patent number: 8134868
    Abstract: Memory devices and methods are disclosed, such as those facilitating data line shielding by way of capacitive coupling with data lines coupled to a memory string source line. For example, alternating data lines are sensed while adjacent data lines are coupled to a common source line of the data lines being sensed. Data line shielding methods and apparatus disclosed can reduce effects of source line bounce occurring during a sense operation of a memory device.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: March 13, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Uday Chandrasekhar
  • System and method for level shifter
    Patent number: 8130558
    Abstract: In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the write path share at least one component.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: March 6, 2012
    Assignee: Infineon Technologies AG
    Inventors: Thomas Nirschl, Jan Otterstedt, Michael Bollu, Wolf Allers
  • Method and device for transmitting outgoing useful signals and an outgoing clock signal
    Patent number: 8125812
    Abstract: Method and device for transmitting outgoing useful signals and an outgoing clock signal. Useful signals and a clock signal are transmitted from a transmitter via a first line pair and a second line pair to a receiver. A first useful signal is transmitted in the form of a modulated difference between the electrical potentials of the first line pair. A second useful signal is transmitted in the form of a modulated difference between the electrical potentials of the second line pair. The clock signal is transmitted in the form of a modulated difference between the average value of the potentials of the first line pair and the average value of the potentials of the second line pair.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: February 28, 2012
    Assignee: Qimonda AG
    Inventors: Martin Streibl, Peter Gregorius, Ralf Schledz
  • Apparatus, system and method for prefetching data in bus system
    Patent number: 8127108
    Abstract: A method for prefetching data in a bus system is provided. First, according to an address signal from a master, a prefetching address generator generates a prefetching address signal and transfers it to a first select circuit. In response to a signal from the master indicates that the address is related to the previous address and the control signal is identical to the previous transfer, or in response to a signal from the master indicates that the address and control signals are unrelated to the previous transfer but is matched to a hit logic, a prefetching controller directs the first select circuit to transfer the prefetching address signal to a slave. And the prefetching controller also directs a second select circuit to transfer the prefetched data which is corresponding to the prefetching address signal from the slave to a master.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: February 28, 2012
    Assignee: Via Technologies, Inc.
    Inventor: Haihui Xu