Abstract: This application relates to container storage management methods and apparatuses. An example method is used to manage a containerized application. The containerized application is deployed in a first container cluster. The first container cluster includes a plurality of nodes. The method includes collecting a plurality of pieces of storage association information from the plurality of nodes. The storage association information is information related to data storage of the containerized application. The method further includes summarizing the plurality of pieces of storage association information to obtain a storage topology of the containerized application. The storage topology of the containerized application includes an association between an element of the containerized application and a physical storage location of the containerized application.

Abstract: A memory sub-system controller selectively adjusts read threshold voltages on certain word lines for partially written memory blocks of a memory sub-system. The controller generates a request to read a portion of a set of memory components. The controller, in response to determining that the portion corresponds to a partially programmed block (PB), selectively modifies a boundary word line (WL) read level offset, stored in a boundary WL offset table, by applying an adjustment factor to the boundary WL read level offset. The controller reads a first set of data from one or more inner WLs of the portion using a first read level offset retrieved from an inner WL offset table and reads a second set of data from a boundary WL of the portion using the selectively modified boundary WL read level offset.

Abstract: In a server system, a host computing platform can have a processing unit separate from the host processor to detect and respond to failure of the host processor. The host computing platform includes a memory to store data for the host processor. The processing unit has an interface to the host processor and the memory and an interface to a network external to the host processor and has access to the memory. In response to detection of failure of the host processor, the processing unit migrates data from the memory to another memory or storage.

Abstract: Various implementations described herein relate to systems and methods for managing superblocks, including determining superblocks, including first and second superblocks, in a non-volatile memory storage. The non-volatile memory storage includes independent locations that may be planes or dies. The first superblock includes first blocks corresponding to first independent locations, and the second superblock includes second blocks corresponding to second independent locations. A first number of the first independent locations is less than a number of the independent locations. A second number of the second plurality of independent locations is less than the number of the independent locations.

Abstract: Systems, methods, and storage adapters for managing queue limits by offloading storage adapter submission queues to the controller memory buffers of data storage devices are described. The storage adapter may receive host storage commands from host devices in one format and provide those host storage commands to the data storage devices in another format for processing. The storage adapter may use submission queues in the controller memory buffers to store the host storage commands until it can preprocess them between the two formats and then notify the data storage device that the host storage command is available for processing.

Abstract: A data processing method and apparatus are disclosed. The data processing method comprises: receiving a data processing request, wherein the data processing request carries target data; generating, based on the target data, a data preprocessing request for the target data; sending the data preprocessing request to at least two data storage modules respectively; in a case where a preprocessing completion notification returned by each data storage module in response to the data preprocessing request is received, sending the data processing request to each data storage module; and receiving a data processing completion notification returned by each data storage module in response to the data processing request. The method ensures the data consistency of each data storage module, further avoiding the problem of data loss in a case where any data storage module of at least two data storage modules fails, thereby ensuring the security of data.

Abstract: A controller of the solid-state drive (SSD) maintains a logical-to-physical translation layer, wherein metadata for the logical-to-physical translation layer is stored in metadata pages in a flash memory of the SSD. The controller tracks a write heat of the metadata pages. The controller stores relatively more frequently accessed metadata pages in a non-durable cache of the SSD. The controller prioritized metadata write operations based on write heat of the metadata pages, such that a NAND flash block of the flash memory contains metadata pages with a similar write heat, wherein extents with similar write heats are grouped together into a stripe that stores extent data, and wherein write heats of the extents with the similar write heats do not differ from each other beyond a predetermined threshold.

Abstract: When execution of a write-back operation is selected, a storage system stores, in a cache area, data for which a write request is issued from a higher-level apparatus, stores an updated content of the cache area in a cache log storage area, and then writes the data to a data storage area. On the other hand, when execution of a write-through operation is selected, the storage system does not execute storage into the cache area and the cache log storage area, stores an updated content of the data storage area in a write log storage area, and then writes the data to the data storage area.

Abstract: A method facilitating memory-aware input batch processing for large language models includes monitoring, by a system including at least one processor, an amount of memory, utilized by a process in execution by a language model in association with processing a first batch of prompts, relative to an available amount of memory for the process in execution; in response to determining that the amount of memory utilized by the process in execution is at least a threshold proportion of the available amount of memory, removing, by the system, at least one prompt from the first batch of prompts according to a priority criterion, resulting in a second batch of prompts; and facilitating, by the system in response to the removing, restarting the process in execution with the second batch of prompts instead of the first batch of prompts.

Abstract: A memory management method is provided for a rewritable non-volatile memory module. The method includes: initiating a data merging operation; selecting a source physical unit and a target physical unit from the rewritable non-volatile memory module to perform the data merging operation; determining whether to create a backup table corresponding to a logical-to-physical mapping table; if it is determined to create the backup table, copying first data located at a first physical address in the source physical unit to a second physical address in the target physical unit, and recording the second physical address in the backup table; and determining whether to update the second physical address to the logical-to-physical mapping table based on information in the backup table.

Abstract: Apparatus and methods are disclosed, including providing available data operations for the storage system processor to a host processor, identifying data operations to be performed by the storage system processor, and assigning identified data operations to the storage system processor to reduce bus traffic between the host processor and the storage system processor, to improve host processor performance, and to reduce energy use by the host processor.

Abstract: A memory module may include a management bus and a plurality of memories connected in series and connected to the management bus, each of the plurality of memories including an identification (ID) input terminal and an ID output terminal. Among the plurality of memories, a memory, for which an activation signal is applied to an ID input terminal of the memory, may set an ID for the memory in response to ID setting information transmitted on the management bus.

Abstract: A host is coupled with a memory system supporting a flexible data placement function. The memory system includes a memory device including K dies. The K dies are divided into L reclaim groups, and each reclaim group includes at least one die. K and L are positive integers greater than or equal to 2. The host includes a user layer and a scheduler. The user layer is configured to send N write requests each corresponding reclaim group information. N is a positive integer. The scheduler is configured to receive the N write requests, and place the N write requests in M request sets. Write requests carrying the same reclaim group information are placed in different ones of the request sets. M is a positive integer less than or equal to N.

Abstract: Apparatuses, systems, and techniques to facilitate memory management. In at least one embodiment, an application programming interface is performed to cause physical memory corresponding to shared virtual memory to be designated for use by a plurality of processors.

Abstract: A storage adapter includes a carrier and a storage device. The storage device stores data and includes a buffer memory including a volatile memory, a nonvolatile memory, a memory controller that controls the buffer memory and the nonvolatile memory, and a mode signal generating circuit that generates a mode signal, based on a connection state of the storage device and the carrier. The carrier removably receives the storage device, and based on a level of the mode signal, the memory controller selectively performs a data dump operation such that the data stored in the buffer memory are stored in the nonvolatile memory.

Abstract: A system and methods are provided for implementing a selected segment size of a shared memory object in a paged-segmented operating system. A user selected shared memory object autonomic promotion feature enables a selected segment size of a shared memory object for a user application. A paged-segmented operating system receiving a request for a shared memory object of a user application, accesses the user selected shared memory object autonomic promotion feature to identify a user selection. An identified user selection is evaluated with secondary criteria for the request shared memory object for the user application and a segment size is set. The operating system creates a shared memory object with the set segment size for the user application. Enabling shared memory objects to be supported by a large segment size reduces the number of segments used for a single shared memory object and application performance can be significantly improved.

Abstract: A storage device includes a non-volatile memory device, a buffer memory configured to store a plurality of meta data blocks and journal data corresponding to the plurality of meta data blocks, the journal data includes a plurality of journal entries indicating update information on the meta data included in one of the plurality of meta data blocks, and a memory controller configured to determine a recovery time of the plurality of meta data blocks based on journal times corresponding to each of the journal entries, the recovery time being a predicted time for recovering the plurality of meta data blocks using the journal data, and perform a meta writing based on the recovery time, the meta writing including writing one of the plurality of meta data blocks to the non-volatile memory device and writing the journal data to the non-volatile memory device.

Abstract: A data management and storage (DMS) cluster of peer DMS nodes manages data of a tenant of a multi-tenant compute infrastructure. The compute infrastructure includes an envoy connecting the DMS cluster to virtual machines of the tenant executing on the compute infrastructure. The envoy provides the DMS cluster with access to the virtual tenant network and the virtual machines of the tenant connected via the virtual tenant network for DMS services such as data fetch jobs to generate snapshots of the virtual machines. The envoy sends the snapshot from the virtual machine to a peer DMS node via the connection for storage within the DMS cluster. The envoy provides the DMS cluster with secure access to authorized tenants of the compute infrastructure while maintaining data isolation of tenants within the compute infrastructure.

Abstract: A gaming device includes a display device, a processor circuit, a battery charging circuit that is conductively coupled to a cabinet input power source and that provides a charging current to a battery, and a power state output signal that is transmitted to the processor circuit and that includes a value that depends on the first switching power input. The device further includes a controller that receives, from the processor circuit, an interrupt signal that indicates that first switching power has failed and transmits a switch signal to the power switching circuit that is caused to switch from providing power from the cabinet input power source to providing power from the battery, a first memory that includes operating memory instructions, and a second memory that is configured to receive the operating memory instructions from the first memory responsive to the interrupt signal indicating that first switching power has failed.

Abstract: A memory device includes a memory cell array configured to store data, a page buffer circuit configured to store data in the memory cell array or read data stored in the memory cell array, and a scan register circuit configured to receive a pass/fail result of data from the page buffer circuit and store the pass/fail result in a plurality of scan registers. The scan register circuit obtains information about the scan register where the fail result is stored through a scan operation, and uses the information about the scan register where the fail result is stored to determine the number of fail bits and/or a position index indicating the position of the fail bits according to the operation mode.