Patents Examined by Daniel D Tsui
  • Patent number: 12639204
    Abstract: A method facilitating memory-aware input batch processing for large language models includes monitoring, by a system including at least one processor, an amount of memory, utilized by a process in execution by a language model in association with processing a first batch of prompts, relative to an available amount of memory for the process in execution; in response to determining that the amount of memory utilized by the process in execution is at least a threshold proportion of the available amount of memory, removing, by the system, at least one prompt from the first batch of prompts according to a priority criterion, resulting in a second batch of prompts; and facilitating, by the system in response to the removing, restarting the process in execution with the second batch of prompts instead of the first batch of prompts.
    Type: Grant
    Filed: November 19, 2024
    Date of Patent: May 26, 2026
    Assignee: DELL PRODUCTS L.P.
    Inventor: Shibi Panikkar
  • Patent number: 12625619
    Abstract: A memory management method is provided for a rewritable non-volatile memory module. The method includes: initiating a data merging operation; selecting a source physical unit and a target physical unit from the rewritable non-volatile memory module to perform the data merging operation; determining whether to create a backup table corresponding to a logical-to-physical mapping table; if it is determined to create the backup table, copying first data located at a first physical address in the source physical unit to a second physical address in the target physical unit, and recording the second physical address in the backup table; and determining whether to update the second physical address to the logical-to-physical mapping table based on information in the backup table.
    Type: Grant
    Filed: October 23, 2024
    Date of Patent: May 12, 2026
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Yen Chen Yeh
  • Patent number: 12613662
    Abstract: Apparatus and methods are disclosed, including providing available data operations for the storage system processor to a host processor, identifying data operations to be performed by the storage system processor, and assigning identified data operations to the storage system processor to reduce bus traffic between the host processor and the storage system processor, to improve host processor performance, and to reduce energy use by the host processor.
    Type: Grant
    Filed: October 14, 2024
    Date of Patent: April 28, 2026
    Inventor: Sebastien Andre Jean
  • Patent number: 12613660
    Abstract: A host is coupled with a memory system supporting a flexible data placement function. The memory system includes a memory device including K dies. The K dies are divided into L reclaim groups, and each reclaim group includes at least one die. K and L are positive integers greater than or equal to 2. The host includes a user layer and a scheduler. The user layer is configured to send N write requests each corresponding reclaim group information. N is a positive integer. The scheduler is configured to receive the N write requests, and place the N write requests in M request sets. Write requests carrying the same reclaim group information are placed in different ones of the request sets. M is a positive integer less than or equal to N.
    Type: Grant
    Filed: July 23, 2024
    Date of Patent: April 28, 2026
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Tianyi Wang, Mo Cheng
  • Patent number: 12613797
    Abstract: A memory module may include a management bus and a plurality of memories connected in series and connected to the management bus, each of the plurality of memories including an identification (ID) input terminal and an ID output terminal. Among the plurality of memories, a memory, for which an activation signal is applied to an ID input terminal of the memory, may set an ID for the memory in response to ID setting information transmitted on the management bus.
    Type: Grant
    Filed: May 9, 2024
    Date of Patent: April 28, 2026
    Assignee: SK hynix Inc.
    Inventors: Choung Ki Song, Kyung Whan Kim, Min Su Park
  • Patent number: 12608320
    Abstract: Apparatuses, systems, and techniques to facilitate memory management. In at least one embodiment, an application programming interface is performed to cause physical memory corresponding to shared virtual memory to be designated for use by a plurality of processors.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: April 21, 2026
    Assignee: NVIDIA Corporation
    Inventors: James Christopher Beyer, Paul J. Sidenblad, Vyas Venkataraman, Chetan Gokhale, Cory Perry, Ying Liang, Harold Carter Edwards
  • Patent number: 12596486
    Abstract: A storage adapter includes a carrier and a storage device. The storage device stores data and includes a buffer memory including a volatile memory, a nonvolatile memory, a memory controller that controls the buffer memory and the nonvolatile memory, and a mode signal generating circuit that generates a mode signal, based on a connection state of the storage device and the carrier. The carrier removably receives the storage device, and based on a level of the mode signal, the memory controller selectively performs a data dump operation such that the data stored in the buffer memory are stored in the nonvolatile memory.
    Type: Grant
    Filed: June 27, 2024
    Date of Patent: April 7, 2026
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Hun Jun, Sung Chul Hur, Bumjun Kim, Jungmoo Son
  • Patent number: 12596478
    Abstract: A system and methods are provided for implementing a selected segment size of a shared memory object in a paged-segmented operating system. A user selected shared memory object autonomic promotion feature enables a selected segment size of a shared memory object for a user application. A paged-segmented operating system receiving a request for a shared memory object of a user application, accesses the user selected shared memory object autonomic promotion feature to identify a user selection. An identified user selection is evaluated with secondary criteria for the request shared memory object for the user application and a segment size is set. The operating system creates a shared memory object with the set segment size for the user application. Enabling shared memory objects to be supported by a large segment size reduces the number of segments used for a single shared memory object and application performance can be significantly improved.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: April 7, 2026
    Assignee: International Business Machines Corporation
    Inventors: Jaime Jaloma, Mark Rogers, Arnold Flores, Mysore S. Srinivas
  • Patent number: 12591372
    Abstract: A storage device includes a non-volatile memory device, a buffer memory configured to store a plurality of meta data blocks and journal data corresponding to the plurality of meta data blocks, the journal data includes a plurality of journal entries indicating update information on the meta data included in one of the plurality of meta data blocks, and a memory controller configured to determine a recovery time of the plurality of meta data blocks based on journal times corresponding to each of the journal entries, the recovery time being a predicted time for recovering the plurality of meta data blocks using the journal data, and perform a meta writing based on the recovery time, the meta writing including writing one of the plurality of meta data blocks to the non-volatile memory device and writing the journal data to the non-volatile memory device.
    Type: Grant
    Filed: March 13, 2024
    Date of Patent: March 31, 2026
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyunsub Kim
  • Patent number: 12591385
    Abstract: A data management and storage (DMS) cluster of peer DMS nodes manages data of a tenant of a multi-tenant compute infrastructure. The compute infrastructure includes an envoy connecting the DMS cluster to virtual machines of the tenant executing on the compute infrastructure. The envoy provides the DMS cluster with access to the virtual tenant network and the virtual machines of the tenant connected via the virtual tenant network for DMS services such as data fetch jobs to generate snapshots of the virtual machines. The envoy sends the snapshot from the virtual machine to a peer DMS node via the connection for storage within the DMS cluster. The envoy provides the DMS cluster with secure access to authorized tenants of the compute infrastructure while maintaining data isolation of tenants within the compute infrastructure.
    Type: Grant
    Filed: October 22, 2024
    Date of Patent: March 31, 2026
    Assignee: Rubrik, Inc.
    Inventors: Abdul Jabbar Abdul Rasheed, Soham Mazumdar, Hardik Vohra, Mudit Malpani
  • Patent number: 12585392
    Abstract: A gaming device includes a display device, a processor circuit, a battery charging circuit that is conductively coupled to a cabinet input power source and that provides a charging current to a battery, and a power state output signal that is transmitted to the processor circuit and that includes a value that depends on the first switching power input. The device further includes a controller that receives, from the processor circuit, an interrupt signal that indicates that first switching power has failed and transmits a switch signal to the power switching circuit that is caused to switch from providing power from the cabinet input power source to providing power from the battery, a first memory that includes operating memory instructions, and a second memory that is configured to receive the operating memory instructions from the first memory responsive to the interrupt signal indicating that first switching power has failed.
    Type: Grant
    Filed: June 7, 2024
    Date of Patent: March 24, 2026
    Assignee: IGT
    Inventors: Wayne Forsey, Michael Patrick, Patrick Russell
  • Patent number: 12579061
    Abstract: A memory device includes a memory cell array configured to store data, a page buffer circuit configured to store data in the memory cell array or read data stored in the memory cell array, and a scan register circuit configured to receive a pass/fail result of data from the page buffer circuit and store the pass/fail result in a plurality of scan registers. The scan register circuit obtains information about the scan register where the fail result is stored through a scan operation, and uses the information about the scan register where the fail result is stored to determine the number of fail bits and/or a position index indicating the position of the fail bits according to the operation mode.
    Type: Grant
    Filed: October 14, 2024
    Date of Patent: March 17, 2026
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Makoto Hirano, Sang Soo Park, Seoyeon Choi, Jae-Duk Yu
  • Patent number: 12566606
    Abstract: Prefetch circuitry may be configured to transmit a message to prefetch one or more cache blocks of a group. The message may indicate an address for the group of cache blocks and a bit field that indicates the one or more cache blocks of the group to prefetch. In some implementations, the message may target a higher level cache to prefetch the one or more cache blocks, and the message may be transmitted to the higher level cache via a lower level cache. In some implementations, the message may target a higher level cache to prefetch the one or more cache blocks, the message may be transmitted to a lower level cache via a first command bus, and the lower level cache may forward the message to the higher level cache via a second command bus.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: March 3, 2026
    Assignee: SiFive, Inc.
    Inventors: Eric Andrew Gouldey, Wesley Waylon Terpstra, Michael Klinglesmith
  • Patent number: 12561098
    Abstract: A method according to one approach is for organizing blocks in a non-volatile storage controller. The method includes: forming a write stripe using a single block from channels of the non-volatile storage. First and second logical erase units are also formed by grouping the blocks from the formed write stripe into at least first and second sub-stripes. The first sub-stripe is assigned to store new data, and the second sub-stripe is assigned to store relocation data. Moreover, writing data to the respective sub-stripes is performed sub-page stripe by sub-page stripe.
    Type: Grant
    Filed: November 15, 2024
    Date of Patent: February 24, 2026
    Assignee: International Business Machines Corporation
    Inventors: Roman Alexander Pletka, Nikolaos Papandreou, Radu Ioan Stoica, Charalampos Pozidis
  • Patent number: 12547322
    Abstract: A first namespace is generated on a particular storage device of the plurality of storage devices for storing configuration data for a storage system. The first namespace is accessible by one or more storage controllers of the storage system. A second namespace is generated on the particular storage device for storing other data at the particular storage device. The configuration data is stored in the first namespace and the other data is stored in the second namespace.
    Type: Grant
    Filed: September 4, 2024
    Date of Patent: February 10, 2026
    Assignee: PURE STORAGE, INC.
    Inventors: Andrew Bernat, Guillaume Girard
  • Patent number: 12547331
    Abstract: Disclosed in the present application are a storage format conversion method, system and apparatus, and an electronic device and a storage medium, which are applied to the technical field of storage. The method is applied to a coprocessor. The method comprises: acquiring row storage page data and configuration information, which are sent by a main processor, wherein the configuration information comprises format information of each column field in a row storage page; parsing the row storage page data according to the configuration information, so as to obtain a column descriptor, wherein the column descriptor comprises a first offset address and field length of each column field in the row storage page; performing calculation according to the column descriptor, so as to obtain filling information related to a column storage page.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: February 10, 2026
    Assignee: IEIT SYSTEMS CO., LTD.
    Inventor: Ke Liu
  • Patent number: 12541305
    Abstract: According to one embodiment, in a case where an error has occurred in reading a first content, a processor of a cache server calculates a delivery capability of the cache server. In a case where it is determined that the calculated delivery capability exceeds a first reference value, the processor does not execute recovering the first content. In a case where it is determined that the calculated delivery capability does not exceed the first reference value, the processor executes recovering the first content, delivering the recovered first content to a client via a network, and writing the recovered first content to a nonvolatile memory.
    Type: Grant
    Filed: September 10, 2024
    Date of Patent: February 3, 2026
    Assignee: Kioxia Corporation
    Inventors: Tatsuki Izumi, Kohei Okuda, Shinichi Kanno
  • Patent number: 12535962
    Abstract: Various embodiments provide for deferring adjustment of a zone in a memory system or sub-system that supports zones. In particular, some embodiments provide for deferred adjustment of a zone based on detection of an error in a block of an unassigned block set, which can be tracked using a counter.
    Type: Grant
    Filed: May 15, 2024
    Date of Patent: January 27, 2026
    Assignee: Micron Technology, Inc.
    Inventors: Oyvind Haehre, Nathaniel Wessel, Byron Harris
  • Patent number: 12530264
    Abstract: In some examples, a cluster protection system comprises at least one processor and a memory storing instructions which, when executed by the at least one processor, cause the system to perform operations comprising identifying a target cluster or an object in a container management framework, identifying application data and metadata associated with the target cluster or the object, generating a first snapshot of the target cluster or the object, the first snapshot including at least the metadata, storing the first snapshot in offsite cloud storage, generating a second snapshot of the target cluster, the second snapshot including at least the application data, and storing the second snapshot in a persistent volume in onsite storage.
    Type: Grant
    Filed: June 27, 2024
    Date of Patent: January 20, 2026
    Assignee: Rubrik, Inc.
    Inventors: Guilherme Vale Ferreira Menezes, Nohhyun Park, Abhishek Dharmaprikar, Rajath Subramanyam, Pin Zhou, Gaurav Khandelwal, Jiangbin Luo
  • Patent number: 12530265
    Abstract: In response to detecting an inability to retrieve a first portion of a first title of content from a primary server using a first resource identifier (locator) value, a communication management resource associated with the communication device switches to use of a second resource identifier (locator) value to retrieve the first portion of the first title of content from a backup server. The communication management resource monitors passage of time in response to the detected inability. During the monitoring and switch over, the communication management resource retrieves segments of content from the backup server. Based on the monitored passage of time, such as after a predetermined time duration, the communication management resource eventually attempts to retrieve another portion of the first title of content from the primary server again using the first resource identifier value as an alternative to use of the second resource identifier value.
    Type: Grant
    Filed: July 16, 2024
    Date of Patent: January 20, 2026
    Assignee: Charter Communications Operating, LLC
    Inventors: Jason M. Donovan, Nikhil H. Parikh