Patents Examined by Daniel D Tsui
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Patent number: 12730754Abstract: An integrated circuit data processing system comprises a plurality of request nodes, a plurality of DVM nodes, assignment logic, an interconnect system and a first chip-to-chip gateway. A first request node is configured to send a DVM message to the DVM node, and the DVM node is configured, in response, to send a first category of snoop message to one or more peer DVM nodes. A second DVM node, is configured, in response, to send a second category of snoop message to request nodes within the domain of the second DVM node and a third category of snoop message to a DVM node of a second integrated circuit. The first chip-to-chip gateway is configured, upon receipt of a snoop message from the second integrated circuit, to send a DVM message to the second DVM node, and the second DVM node is configured, in response, to send a fourth category of snoop message to one or more peer DVM nodes.Type: GrantFiled: March 5, 2025Date of Patent: September 8, 2026Assignee: Arm LimitedInventors: Ashok Kumar Tummala, Leif Christian Bagge, Randall John Pascarella, Jamshed Jalal, Christopher William Laycock, Pranav Lalan, Rushit Umesh Shah
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Patent number: 12724547Abstract: A method of storing data includes: writing data in a first buffer area and writing data in a second buffer area of a page buffer; writing data in a third buffer area of the page buffer, wherein the data written in the third buffer area are obtained by taking a computation resource of the page buffer to perform a logical operation on the data in the first buffer area and the data in the second buffer area; first data information is determined based on the data in the first buffer area, the data in the second buffer area, and the data in the third buffer area; and writing the first data information cached in the page buffer to a memory unit.Type: GrantFiled: November 18, 2024Date of Patent: September 1, 2026Assignee: Shanghai Longsys Digital Technology Co., LimitedInventors: Weizhen Kong, Xinghui Duan
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Patent number: 12724536Abstract: A frontend data segment storing a memory address that corresponds to data to be written to a block associated with a blockstripe is received from a frontend processing device. Responsive to receiving the frontend data segment, a backend data segment is generated. Data associated with a plurality of blocks, including the block, is read from a memory device. One or more memory addresses that correspond to the data that is associated with the plurality of blocks are stored in the backend data segment. The frontend data segment is updated with the one or more memory addresses that correspond to the data that is associated with the plurality of blocks. A programming operation is performed using the updated frontend data segment.Type: GrantFiled: February 20, 2025Date of Patent: September 1, 2026Assignee: Micron Technology, Inc.Inventor: Jessie Ji
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Patent number: 12717496Abstract: There are provided a system and a method for write or store driven buffer cache memory for a Reliable Array of Independent Disks (RAID)-protected memory. For example, there is provided a system that can include a RAID subsystem configured to maintain the integrity of a section of a memory. The system can further include a buffer memory communicatively coupled to the RAID subsystem. And the RAID subsystem may be configured to limit a frequency of RAID access memory command amplification by accessing the buffer memory the subsystem is performing an operation configured to maintain the integrity of the section of the memory.Type: GrantFiled: June 26, 2024Date of Patent: August 25, 2026Assignee: Micron Technology, Inc.Inventors: Edmund Gieske, Dhawal Bavishi, Robert M. Walker
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Patent number: 12717497Abstract: Various embodiments provide handling block read-verify failure in a memory sub-system that supports zones. In particular, some embodiments described herein handle block read-verify failure during migration (e.g., copyback) of data from one or more cache blocks to one or more non-cache blocks of a zone on a memory device on a memory sub-system, during non-cache block (e.g., QLC non-cache block) refresh, or both.Type: GrantFiled: July 30, 2024Date of Patent: August 25, 2026Assignee: Micron Technology, Inc.Inventors: Juane Li, Amit Bhardwaj, Michael Winterfeld
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Patent number: 12710895Abstract: Techniques are provided for implementing write ordering for persistent memory. A set of actions are identified for commitment to persistent memory of a node for executing an operation upon the persistent memory. An episode is created to comprise a first subset of actions of the set of actions that can be committed to the persistent memory in any order with respect to one another such that a consistent state of the persistent memory can be reconstructed in the event of a crash of the node during execution of the operation. The first subset of actions within the episode are committed to the persistent memory and further execution of the operation is blocked until the episode completes.Type: GrantFiled: November 11, 2024Date of Patent: August 18, 2026Assignee: NetApp, Inc.Inventors: Ram Kesavan, Matthew Fontaine Curtis-Maury, Abdul Basit, Vinay Devadas, Ananthan Subramanian
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Patent number: 12705149Abstract: A first set of blocks of storage memory is allocated as durable and a second set of blocks of the storage memory is allocated as semi-durable. The durable first set of blocks are provided power loss protection (PLP) and the semi-durable second set of blocks lack PLP. Data generated by one or more background operations of the storage system is identified. The data generated by the one or more background operations is stored in one or more blocks of the semi-durable second set of blocks.Type: GrantFiled: June 25, 2024Date of Patent: August 11, 2026Assignee: EVERPURE, INC.Inventors: Ronald Karr, Matthew Davis, Riley Thomasson, Andrew Bernat
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Patent number: 12704972Abstract: An apparatus with a solid state drive (SSD) having firmware to farm proof of space plots stored outside of the SSD. The SSD has a communication interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. The firmware is executable in the SSD to receive and store configuration data specified via a user interface to indicate a location, outside of the SSD, storing a proof of space plot that can be used by the SSD to participate in proof of space activities in a cryptocurrency network.Type: GrantFiled: April 2, 2024Date of Patent: August 11, 2026Assignee: Micron Technology, Inc.Inventors: Joseph Harold Steinmetz, Luca Bert
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Patent number: 12693782Abstract: A computational storage device includes a control module, and a nonvolatile memory connected to the control module. The nonvolatile memory is configured to store a plurality of graph data elements, which comprises a plurality of nodes and a plurality of edges that connect at least a portion of the plurality of nodes to each other, in a first memory area and a second memory area each having a plurality of blocks and having different read speeds. The control module is configured to store a first graph data element of the plurality of graph data elements having a relatively high degree of association with one node of the plurality of nodes in the first memory area, and store a second graph data element of the plurality of graph data elements having a relatively low degree of association with the one node of the plurality of nodes in the second memory area.Type: GrantFiled: October 22, 2024Date of Patent: July 28, 2026Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hwa Jin, Min-Ho Kim, Dongouk Moon, Soo-Young Ji
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Patent number: 12693796Abstract: A program command specifying new data to be programmed is received and partitioned into a plurality of data partitions. A wordline addressing a first set of memory cells to be programmed with a data partition of the plurality of data partitions is identified for a specified block of the memory device. Existing data stored by a second set of memory cells is read. An expected data state metrics is produced for each data partition of the plurality of data partitions. A data partition associated with a lowest expected data state metric among the plurality of expected data state metrics is identified. The identified data partition is programmed to the identified wordline.Type: GrantFiled: December 4, 2024Date of Patent: July 28, 2026Assignee: Micron Technology, Inc.Inventors: Yu-Chung Lien, Zhenming Zhou
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Patent number: 12681647Abstract: This application relates to container storage management methods and apparatuses. An example method is used to manage a containerized application. The containerized application is deployed in a first container cluster. The first container cluster includes a plurality of nodes. The method includes collecting a plurality of pieces of storage association information from the plurality of nodes. The storage association information is information related to data storage of the containerized application. The method further includes summarizing the plurality of pieces of storage association information to obtain a storage topology of the containerized application. The storage topology of the containerized application includes an association between an element of the containerized application and a physical storage location of the containerized application.Type: GrantFiled: September 30, 2024Date of Patent: July 14, 2026Assignee: Huawei Technologies Co., Ltd.Inventors: Ming Li, Xiaokang He
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Patent number: 12675224Abstract: A memory sub-system controller selectively adjusts read threshold voltages on certain word lines for partially written memory blocks of a memory sub-system. The controller generates a request to read a portion of a set of memory components. The controller, in response to determining that the portion corresponds to a partially programmed block (PB), selectively modifies a boundary word line (WL) read level offset, stored in a boundary WL offset table, by applying an adjustment factor to the boundary WL read level offset. The controller reads a first set of data from one or more inner WLs of the portion using a first read level offset retrieved from an inner WL offset table and reads a second set of data from a boundary WL of the portion using the selectively modified boundary WL read level offset.Type: GrantFiled: July 31, 2024Date of Patent: July 7, 2026Assignee: Micron Technology, Inc.Inventors: Christina Papagianni, Murong Lang, Guang Hu
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Patent number: 12669943Abstract: In a server system, a host computing platform can have a processing unit separate from the host processor to detect and respond to failure of the host processor. The host computing platform includes a memory to store data for the host processor. The processing unit has an interface to the host processor and the memory and an interface to a network external to the host processor and has access to the memory. In response to detection of failure of the host processor, the processing unit migrates data from the memory to another memory or storage.Type: GrantFiled: September 26, 2022Date of Patent: June 30, 2026Assignee: Intel CorporationInventors: Karthik Kumar, Francesc Guim Bernat, Alexander Bachmutsky, Susanne M. Balle, Andrzej Kuriata, Nagabhushan Chitlur
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Patent number: 12663932Abstract: Various implementations described herein relate to systems and methods for managing superblocks, including determining superblocks, including first and second superblocks, in a non-volatile memory storage. The non-volatile memory storage includes independent locations that may be planes or dies. The first superblock includes first blocks corresponding to first independent locations, and the second superblock includes second blocks corresponding to second independent locations. A first number of the first independent locations is less than a number of the independent locations. A second number of the second plurality of independent locations is less than the number of the independent locations.Type: GrantFiled: October 18, 2024Date of Patent: June 23, 2026Assignee: KIOXIA CORPORATIONInventors: Neil Buxton, Steven Wells
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Patent number: 12663945Abstract: Systems, methods, and storage adapters for managing queue limits by offloading storage adapter submission queues to the controller memory buffers of data storage devices are described. The storage adapter may receive host storage commands from host devices in one format and provide those host storage commands to the data storage devices in another format for processing. The storage adapter may use submission queues in the controller memory buffers to store the host storage commands until it can preprocess them between the two formats and then notify the data storage device that the host storage command is available for processing.Type: GrantFiled: December 5, 2024Date of Patent: June 23, 2026Assignee: Western Digital Technologies, Inc.Inventor: Narayan Ayalasomayajula
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Patent number: 12663926Abstract: A data processing method and apparatus are disclosed. The data processing method comprises: receiving a data processing request, wherein the data processing request carries target data; generating, based on the target data, a data preprocessing request for the target data; sending the data preprocessing request to at least two data storage modules respectively; in a case where a preprocessing completion notification returned by each data storage module in response to the data preprocessing request is received, sending the data processing request to each data storage module; and receiving a data processing completion notification returned by each data storage module in response to the data processing request. The method ensures the data consistency of each data storage module, further avoiding the problem of data loss in a case where any data storage module of at least two data storage modules fails, thereby ensuring the security of data.Type: GrantFiled: March 29, 2023Date of Patent: June 23, 2026Assignee: Cloud Intelligence Assets Holding (Singapore) Private LimitedInventors: Yunfeng Zhu, Xiangguang Yan, Shuai Zhao
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Patent number: 12650919Abstract: A controller of the solid-state drive (SSD) maintains a logical-to-physical translation layer, wherein metadata for the logical-to-physical translation layer is stored in metadata pages in a flash memory of the SSD. The controller tracks a write heat of the metadata pages. The controller stores relatively more frequently accessed metadata pages in a non-durable cache of the SSD. The controller prioritized metadata write operations based on write heat of the metadata pages, such that a NAND flash block of the flash memory contains metadata pages with a similar write heat, wherein extents with similar write heats are grouped together into a stripe that stores extent data, and wherein write heats of the extents with the similar write heats do not differ from each other beyond a predetermined threshold.Type: GrantFiled: March 29, 2023Date of Patent: June 9, 2026Assignee: International Business Machines CorporationInventors: Radu Ioan Stoica, Dan Lazar, Timothy J. Fisher, Nikolaos Papandreou, Roman Alexander Pletka, Charalampos Pozidis, Aaron Daniel Fry, Andrew D. Walls
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Patent number: 12650778Abstract: When execution of a write-back operation is selected, a storage system stores, in a cache area, data for which a write request is issued from a higher-level apparatus, stores an updated content of the cache area in a cache log storage area, and then writes the data to a data storage area. On the other hand, when execution of a write-through operation is selected, the storage system does not execute storage into the cache area and the cache log storage area, stores an updated content of the data storage area in a write log storage area, and then writes the data to the data storage area.Type: GrantFiled: September 11, 2024Date of Patent: June 9, 2026Assignee: HITACHI VANTARA, LTD.Inventors: Taisuke Ono, Yoshinori Ohira, Takahiro Yamamoto, Shintaro Ito
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Patent number: 12639204Abstract: A method facilitating memory-aware input batch processing for large language models includes monitoring, by a system including at least one processor, an amount of memory, utilized by a process in execution by a language model in association with processing a first batch of prompts, relative to an available amount of memory for the process in execution; in response to determining that the amount of memory utilized by the process in execution is at least a threshold proportion of the available amount of memory, removing, by the system, at least one prompt from the first batch of prompts according to a priority criterion, resulting in a second batch of prompts; and facilitating, by the system in response to the removing, restarting the process in execution with the second batch of prompts instead of the first batch of prompts.Type: GrantFiled: November 19, 2024Date of Patent: May 26, 2026Assignee: DELL PRODUCTS L.P.Inventor: Shibi Panikkar
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Patent number: 12625619Abstract: A memory management method is provided for a rewritable non-volatile memory module. The method includes: initiating a data merging operation; selecting a source physical unit and a target physical unit from the rewritable non-volatile memory module to perform the data merging operation; determining whether to create a backup table corresponding to a logical-to-physical mapping table; if it is determined to create the backup table, copying first data located at a first physical address in the source physical unit to a second physical address in the target physical unit, and recording the second physical address in the backup table; and determining whether to update the second physical address to the logical-to-physical mapping table based on information in the backup table.Type: GrantFiled: October 23, 2024Date of Patent: May 12, 2026Assignee: PHISON ELECTRONICS CORP.Inventor: Yen Chen Yeh