Abstract: An electronic device includes a processor having processor circuitry and a leader memory controller, a controller coupled to the processor and having a follower memory controller, and a memory. The processor circuitry is operable to access the memory by issuing memory access requests to the leader memory controller. The leader memory controller is operable to complete the memory access requests using the follower memory controller to issue memory commands to the at least one memory die.

Abstract: The disclosure provides techniques for storage device input/output (I/O) performance improvement in a remote computing environment. Embodiments include creating, on a remote device that is remote from a client device, a virtual storage device corresponding to a physical storage device that is located on the client device. Embodiments include receiving, by a driver on the remote device, a request from an application on the remote device to perform an input or output operation with respect to the virtual storage device. Embodiments include sending, by the remote device, a block-level input or output operation to the client device based on the request. Embodiments include receiving, by the remote device, a result of the block-level input or output operation from the client device. Embodiments include providing, by the driver on the remote device, to the application, a response to the request based on the result of the block-level input or output operation.

Abstract: Decoupled computing systems include layers of same-type computing resources, and include a dispatch layer to assign tasks from one layer to another, such as input and output (I/O) flows. The I/O flows can be assigned to particular computing resources of a layer based on a weighted moving average of performance data for the layer. When traffic is high, the assignment can include random assignment to some or all of the computing resources in the layer. The I/O flows can be split between read-intensive and write-intensive flows, with more read-intensive flows being assigned based on a pick ratio.

Abstract: A CXL memory module, a controller, a method for accessing data, and a storage system are provided, which relate to data storage technologies. The CXL memory module includes a controller and a group of memory chips connected to the controller. The controller has a KV interface based on a CXL protocol. The controller is configured to receive a KV instruction sent by an external device through the KV interface, store object-based data into a memory chip or acquire object-based data from a memory chip.

Abstract: A first host data item and a second host data item are received. The first host data item is stored in a first page of a first logical unit of a memory device, where the first page is one of a plurality of pages associated with redundancy metadata. A second page a second page of a second logical unit of the memory device is identified, where the second page is one of the plurality of pages associated with the redundancy metadata, and the first page and the second page are associated with different wordlines of the memory device. The second host data item is stored in the second page of the second logical unit of the memory device. The first page and the second page can be associated with a fault tolerant stripe that includes the redundancy metadata.

Abstract: A method for operating a system including a host and at least one solid state drive (SSD). The method identifies a workload associated with the SSD, recognizes a power state of the SSD, and controls allocation and/or deallocation of hardware resources for the identified workload per a budgeted target for the power state.

Abstract: A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.

Abstract: Systems and method for implementing deduplication process based on performance analyses. The system may include a processing device to determine a first performance metric associated with retrieving a second stored data block that is within a specified range of a duplicate of the first data block and a second performance metric associated with retrieving a hash value corresponding to the second stored data block. The processing device further to retrieve the second stored data block within a specified range of the duplicate of the first data block in response to the first performance metric not exceeding the second performance metric.

Abstract: Presented herein are systems and methods for backing up and restoring related backup data stored in different cloud storage tiers in a cloud storage environment. Backup data generated during a backup job is stored to different cloud storage tiers based on the type of data and a storage policy comprising designations of a first cloud storage tier and a second cloud storage tier. Backup metadata and index data is stored in the designated first cloud storage tier and backup payload data is stored in the designated second cloud storage tier. Designations of the storage tiers are based on the attributes associated with each tier of cloud storage. During restore, the backup payload data is recalled from the second storage tier into the first storage tier where it is used to restore to the destination client or customer.

Abstract: Performance deterioration of a storage system is prevented. A storage controller includes one or more processors, and one or more memories configured to store one or more programs to be executed by the one or more processors. The one or more processors are configured to execute conversion of converting metadata before conversion for controlling the storage system into metadata after conversion in a format corresponding to a new controller newly installed in the storage system, execute control of switching an access destination between the metadata before conversion and the metadata after conversion according to an access control code during the conversion, and access the metadata before conversion without using the access control code before start of the conversion.

Abstract: Instead of using programmable block size aggregation, a lower multiple of page, and down to a page size aggregation is used. A bad block prediction unit in a controller is able to predict when a programmable block has a bad page. The bad block prediction unit can lower the aggregation size of a programmable block by monitoring the life cycle of the programmable block through bad block statistic collection. When the accumulation size passes a threshold, the bad block prediction unit lowers the aggregation size. The bad block prediction unit can also predict when to lower aggregation size based on the number of reconstructions. An aggregate size level is set at a page boundary, and once the number of reconstructions reaches that page boundary, the bad block prediction unit lowers the aggregation size to page aggregation. The bad block prediction unit is able to predict both life cycle threshold changes and reconstructions changes.

Abstract: The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed may include a nonvolatile memory device, a main memory configured to temporarily store data related to controlling the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host. The main memory may aggregate and process a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.

Abstract: A DNA-based storage system uses a set of initial state transition probabilities during a decoding process in which a DNA codeword is decoded. After a threshold number of decoding iterations of the decoding process have been executed, at least one initial state transition probability of the set of initial state transition probabilities is updated. The at least one initial state transition probability is updated based, at least in part, on information obtained during the threshold number of decoding iterations. When the at least one initial state transition probability is updated, the decoding process resumes and uses the updated at least one initial state transition probability.

Abstract: A performance monitor provides cache miss stall and memory bandwidth usage metric samples to a resource exhaustion detector. The detector can detect the presence of last-level cache and memory bandwidth exhaustion conditions based on the metric samples. If cache miss stalls and memory bandwidth usage are both trending up, the detector reports a memory bandwidth exhaustion condition to a resource controller. If cache miss stalls are trending up and memory bandwidth usage is trending down, the detector reports a last-level cache exhaustion condition to the resource controller. The resource controller can allocate additional last-level cache or memory bandwidth to the processor unit to remediate the resource exhaustion condition. If bandwidth-related metric samples indicate that a processor unit may be overloaded due to receiving high bandwidth traffic, the resource controller can take a traffic rebalancing remedial action.

Abstract: Methods, devices, and systems for managing performance of a processor having multiple compute units. An effective number of the multiple compute units may be determined to designate as having priority. On a condition that the effective number is nonzero, the effective number of the multiple compute units may each be designated as a priority compute unit. Priority compute units may have access to a shared cache whereas non-priority compute units may not. Workgroups may be preferentially dispatched to priority compute units. Memory access requests from priority compute units may be served ahead of requests from non-priority compute units.

Abstract: A protected facility (20), including a processor (150) a network (46) and a security module (50) unidirectionally coupling the network to a workstation (34) external to the facility, and configured to carry commands (78) unidirectionally from the workstation to the network and to be incapable of carrying commands in the opposite direction. A storage controller (24) coupled the network is configured to define first and second volumes (64) including respective sets of storage blocks (136), to store data (30) to the first volume, and to expose the second volume workstation (34). The processor is coupled to the network and configured to receive commands only from the workstation via the module, to receive, from the storage controller, access to the data, to receive, from the workstation, a command to train a model (32), to analyze the data to train the model, and to store the trained model to the second volume.

Abstract: A memory sub-system to initiate an erase operation to erase a first set of memory cells of a first memory block and a second set of memory cells of a second memory block of a memory device. One or more erase pulses of the erase operation are caused to be applied to the first set of memory cells of the first memory block and the second set of memory cells of the second memory block concurrently. A first erase verify sub-operation of the erase operation is caused to be performed to verify the first memory block is erased and a second erase verify sub-operation of the erase operation is caused to be performed to verify the second memory block is erased.

Abstract: According to one embodiment, a magnetic disk device includes a plurality of magnetic disks including a first recording surface and a second recording surface, a first magnetic head that writes data to the first recording surface, a second magnetic head that writes data to the second recording surface and a controller that includes a counter configured to detect the number of writes of each of the first magnetic head and the second magnetic head, an unwritten detection unit configured to detect an unwritten block from the blocks, and a memory configured to store a first threshold for the number of writes of each of the first magnetic head and the second magnetic head and a second threshold less than or equal to the first threshold.

Abstract: A peripheral device includes a bus interface and an Address Translation Service (ATS) controller. The bus interface is to communicate over a peripheral bus. The ATS controller is to communicate over the peripheral bus, including sending address translation requests and receiving address translations in response to the address translation requests, to cache at least some of the address translations in one or more Address Translation Caches (ATCs), to estimate one or more statistical properties of the received address translations, and to configure the one or more ATCs based on the one or more statistical properties.

Abstract: A processor configured to control a storage device includes at least one host write buffer generated based on device information of the storage device, and a control module configured to control the at least one host write buffer. The control module is further configured to store, in the at least one host write buffer, a plurality of write commands and merge the plurality of write commands to generate a merged write command.