Patents Examined by Daniel D Tsui
  • Patent number: 10838640
    Abstract: A system and method for utilizing unmapped and unknown states in a storage system. When a first portion of a first medium is determined to be unreachable from any other mediums, the first portion of the first medium may be put into an unmapped state, and its data may be discarded and the corresponding storage locations may be freed. During replication of the first medium to a replica storage array, the state of the first portion of the first medium may be translated from the unmapped state into an unknown state on the replica storage array. If another storage array has the data of the first portion of the first medium, this data may be used to overwrite the first portion of the first medium on the replica storage array, converting the first portion of the first medium from the unknown state into the mapped state.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: November 17, 2020
    Assignee: Pure Storage, Inc.
    Inventors: Christopher Golden, John Colgrove, Ethan L. Miller, Malcolm Sharpe, Steve Hodgson
  • Patent number: 10831682
    Abstract: Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Patrick A. La Fratta, Robert M. Walker
  • Patent number: 10824371
    Abstract: Apparatus and methods are disclosed, including providing available data operations for the storage system processor to a host processor, identifying data operations to be performed by the storage system processor, and assigning identified data operations to the storage system processor to reduce bus traffic between the host processor and the storage system processor, to improve host processor performance, and to reduce energy use by the host processor.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Sebastien Andre Jean
  • Patent number: 10818361
    Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Harish Reddy Singidi, Kishore Kumar Muchherla, Michael G. Miller, Sampath Ratnam, Xu Zhang, Jie Zhou
  • Patent number: 10802726
    Abstract: A garbage collection process running on a computing device is configured to track the number of garbage collection cycles that storage fragments, called extents, are persisted in storage without being modified or deleted using a lifetime counter that is implemented using metadata. At each garbage collection cycle, the extents are sorted by lifetime values. Old extents (i.e., those existing at the start of the cycle) are bucketed together by lifetime values during garbage collection into new extents (i.e., those being created during the cycle). Thus, each of the new extents includes data having similar lifetime values. The lifetime value for the new extent equals the lowest lifetime value of the old source extent plus one additional increment on the counter. As extents are organized by garbage collection lifetime, placement on storage media can be optimized according to expected endurance requirements.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: October 13, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Michael Sean McGrath
  • Patent number: 10783087
    Abstract: Provided are a computer program product, system, and method for using a machine learning module to select one of multiple cache eviction algorithms to use to evict a track from the cache. A first cache eviction algorithm determines tracks to evict from the cache. A second cache eviction algorithm determines tracks to evict from the cache, wherein the first and second cache eviction algorithms use different eviction schemes. At least one machine learning module is executed to produce output indicating one of the first cache eviction algorithm and the second cache eviction algorithm to use to select a track to evict from the cache. A track is evicted that is selected by one of the first and second cache eviction algorithms indicated in the output from the at least one machine learning module.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kyler A. Anderson, Kevin J. Ash
  • Patent number: 10782886
    Abstract: To provide a semiconductor device which suppresses a delay in processing. The semiconductor device is equipped with a plurality of read units which read data stored across a plurality of banks in a memory having the banks, and an access method managing section which, when one of the read units reads the data, determines a read start bank number being a bank number to start reading according to operation situations of the read units excepting the one read unit, and instructs the determined read start bank number to the one read unit.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: September 22, 2020
    Inventors: Nhat Van Huynh, Seiji Mochizuki, Katsushige Matsubara, Toshiyuki Kaya
  • Patent number: 10776278
    Abstract: A storing unit stores therein mapping management information indicating mappings between each of a plurality of divided regions created by dividing logical storage space on a storage apparatus and one of a plurality of identification numbers each representing a different write frequency. A control unit measures the write frequency of each of the plurality of divided regions and updates the mappings indicated by the mapping management information based on results of the write frequency measurement. Upon request for a data write to a write address included in a divided region after the update of the mappings, the control unit identifies an identification number associated with the divided region based on the mapping management information, appends the identified identification number to a write request for the write address, and transmits the write request with the identified identification number appended thereto to the storage apparatus.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: September 15, 2020
    Inventors: Takanori Ishii, Tomoka Aoki
  • Patent number: 10762968
    Abstract: A memory component includes a memory configured to store an updatable trim profile that is user-modifiable. The updatable trim profile includes address information corresponding to a trim register to be modified, command information corresponding to an action to be performed, and data corresponding to the action to be performed. A processing device that is coupled to the memory component is configured to receive an instruction to modify the trim register, read contents of the updatable trim profile, and modify the trim register based on the address information, the action to be performed on the trim register, and the data.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gerald L. Cadloni, Michael Sheperek
  • Patent number: 10761781
    Abstract: Apparatuses and methods for a distributed memory system including memory nodes are disclosed. An example apparatus includes a processor and a memory system coupled to the processor. The memory system is configured to receive instructions from the processor to access information stored by the memory system. The memory system includes a plurality of memory nodes, wherein each memory node of the plurality of memory nodes is coupled to at least one other memory node of the plurality of memory nodes, and each memory node of the plurality of memory nodes is configured to generate an internal message including instructions for an operation, the internal message to be provided to another memory node of the plurality of memory nodes to perform the operation.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth M. Curewitz, Sean E. Eilert
  • Patent number: 10754777
    Abstract: Data units are stored in private caches in nodes of a multiprocessor system, each node containing at feast one processor (CPU), at least one cache private to the node and at least one cache location buffer {CLB} private to the node. In each CLB location information values are stored, each location information value indicating a location associated with a respective data unit, wherein each location information value stored in a given CLB indicates the location to be either a location within the private cache disposed in the same node as the given CLB, to be a location in one of the other nodes, or to be a location in a main memory. Coherence of values of the data units is maintained using a cache coherence protocol The location information values stored in the CLBs are updated by the cache coherence protocol in accordance with movements of their respective data units.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: August 25, 2020
    Inventors: Erik Hagersten, Andreas Sembrant, David Black-Schaffer
  • Patent number: 10740034
    Abstract: Systems, methods, apparatuses, and software for data storage systems are provided herein. In one example, a data storage apparatus includes a processor configured to assign service levels in a queue for handling storage operations directed to one or more data storage drives. The processor can pre-allocate resources in the queue for selected ones of the service levels before ones of the storage operations associated with the selected ones of the service levels are received by the processor. The processor receives the storage operations, and based at least on the service levels, services the storage operations from the queue with the one or more data storage drives.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: August 11, 2020
    Assignee: Liqid Inc.
    Inventors: Phillip Clark, James Scott Cannata, Jason Breakstone
  • Patent number: 10725687
    Abstract: A method for data protection in a memory system includes receiving, from entity, an address range and a set command, the address range corresponding to at least a portion of a memory partition in the memory system. The method further includes determining whether the entity is an authenticated entity. The method further includes based on the determination of whether the entity is an authenticated entity, setting, using the set command, access characteristics of the portion of the partition corresponding to the address range.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: July 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, David Brief, Eliad Adi Klein
  • Patent number: 10713104
    Abstract: A storage system includes: a control processor, configured to: read user data, generate a bit flip array from the user data including limiting a threshold offset range, and select an optimal read threshold set from the bit flip array; and a non-volatile memory array, coupled to the control processor, configured to store the user data; and wherein the control processor is further configured read a sector N with the optimal read threshold set for enhancing performance of the non-volatile memory array.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: July 14, 2020
    Assignee: CNEX LABS, Inc.
    Inventors: Xiaojie Zhang, Yi Liu
  • Patent number: 10705953
    Abstract: A method implemented by a memory device, comprising obtaining, by a processor coupled to a memory, a wear-leveling policy from an application executable at the memory device, wherein the wear-leveling policy indicates a memory size by which to perform wear-leveling within an instance, wherein the instance comprises an address range assigned to the application in the memory of the memory device, obtaining, by a processor, a request to access the instance, and performing, by the processor, wear-leveling on a plurality of memory cells within the instance according to the wear-leveling policy.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: July 7, 2020
    Assignee: Futurewei Technologies, Inc.
    Inventor: Chaohong Hu
  • Patent number: 10698440
    Abstract: A calibration controller determines a latest arriving data strobe at a first data buffer in a read data path between at least one memory chip and a host on a high speed interface. The calibration controller aligns a chip clock distributed to a second data buffer in the read data path with the latest arriving data strobe, wherein data cross a first clock boundary from the first data buffer to the second data buffer, to minimize a latency in the read data path across the first clock boundary. The calibration controller aligns the chip clock with a high speed clock for controlling an unload pointer to unload the data from the second data buffer to a serializer in the read data path, wherein the data cross a second clock boundary from the second data buffer to the serializer, to minimize a latency in the read data path across a second clock boundary.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: June 30, 2020
    Inventors: Steven R. Carlough, Susan M. Eickhoff, Michael B. Spear, Gary A. Van Huben, Stephen D. Wyatt
  • Patent number: 10691370
    Abstract: According to examples, an apparatus may include a processor and a non-transitory machine-readable storage medium comprising instructions executable by the processor to assign a first object identifier and a data identifier to a first volume, the first object identifier being assigned exclusively to the first volume. The instructions may also be executable by the processor to identify an identifier of a second volume, determined whether the identifier of the second volume matches the data identifier, and based on a determination that the identifier of the second volume matches the data identifier of the first volume, configure a replication relationship between the first volume and the second volume.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: June 23, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Praveen Killamsetti, Tomasz Barszczak, Naveen Bali, Michael E. Root
  • Patent number: 10691362
    Abstract: Methods, systems, and computer program products are included for deduplicating one or more memory pages. A method includes receiving a first key from a first application running on a computer system. The method also includes associating the first key with a first memory allocated to the first application and scanning a second memory for duplicate memory pages of the first memory. The second memory is associated with a second key and allocated to a second application running on the computer system. The method also includes in response to a determination that the first and second keys are the same and that a scanned memory page is a duplicate of a first memory page of the first memory, deduplicating the scanned memory page and the first memory page.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: June 23, 2020
    Assignee: Red Hat, Ltd.
    Inventors: Michael Tsirkin, Uri Lublin
  • Patent number: 10635349
    Abstract: A storage device includes nonvolatile memories and a controller. The controller previously manages a correspondence relationship between physical addresses indicating the memory regions and stream identifiers, before first write data is received by the controller. The controller controls the nonvolatile memories such that the first write data is stored in a first memory region of a physical address which is managed corresponding to a first stream identifier of the first write data in the correspondence relationship. The first write data is transferred to the nonvolatile memories based on the correspondence relationship, regardless of whether second write data having a second stream identifier is received by the controller.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: April 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Younggeun Lee, Jinwoo Kim, Youngsik Kim, Hwan-Chung Kim, Jeonghoon Cho
  • Patent number: 10628589
    Abstract: Methods, systems, and computer readable media for preventing code reuse attacks are disclosed. According to one method, the method includes executing, on a processor, code in a memory page related to an application, wherein the memory page is protected. The method also includes detecting a read request associated with the code. The method further includes after detecting the read request, modifying, without using a hypervisor, at least one memory permission associated with the memory page such that the code is no longer executable after the code is read.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: April 21, 2020
    Inventors: Jan Jakub Werner, Kevin Zachary Snow, Nathan Michael Otterness, Robert John Dallara, Georgios Baltas, Fabian Newman Monrose, Michalis Polychronakis