Patents Examined by Daniel D Tsui
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Patent number: 11893247Abstract: The present technology relates to an electronic device. According to the present technology, a data storage device providing an improved security function includes a memory device including a protected memory block by a security protocol and a memory controller configured to receive a command protocol component associated with the security protocol including a host side protection message requesting data from a host to be written in the protected memory block, perform an authentication operation on the protected memory block using a host message authentication code included in the host side protection message, and store data from the host according to a result of the authentication operation.Type: GrantFiled: March 5, 2021Date of Patent: February 6, 2024Assignee: SK HYNIX INC.Inventor: Hui Won Lee
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Patent number: 11886226Abstract: A method of consolidating snapshots includes receiving a request to consolidate a first snapshot with a second snapshot into a third snapshot, the first and second snapshots stored in separate backup files, each backup file organized as a directory where data parts of the first and second snapshots can be hard linked to locations outside of the backup file, comparing the data parts of the first and second snapshots to determine if any second snapshot data part fully overlaps with any first snapshot data part, responsive to determining that a second snapshot data part fully overlaps with a first snapshot data part, hard linking the determined second snapshot data part into the third snapshot, and storing the third snapshot in the backup file.Type: GrantFiled: November 29, 2021Date of Patent: January 30, 2024Assignee: Rubrik, Inc.Inventors: Vijay Karthik, Abdullah Reza
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Patent number: 11886739Abstract: Methods, systems, and devices for a read operation using compressed memory are described. An apparatus may include a host system coupled with a non-volatile memory device and a volatile memory device. The host system may store, in the volatile memory device, a compressed copy of data stored in the non-volatile memory device, for example, based on a score assigned to the data. The host system may identify that the compressed copy of the data is stored in the volatile memory device and may transmit a read command to the volatile memory device that includes a logical address associated with a logical block address of the data stored in the non-volatile memory device. The host system may receive the compressed copy of the data from the volatile memory device in response to the read command and may decompress the data.Type: GrantFiled: January 8, 2021Date of Patent: January 30, 2024Assignee: Micron Technology, Inc.Inventors: Venkata Kiran Kumar Matturi, Tushar Chhabra, Sushil Kumar, Sharath Chandra Ambula
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Patent number: 11875060Abstract: Data replication techniques can include receiving, at a source system, a write directed to a source logical device configured for asynchronous remote replication to a destination system; performing processing that flushes a transaction log entry for the write; and performing replication processing that uses a replication queue including a replication queue entry corresponding to the write that stores the first content to a logical address. The processing can create a replication log entry in a replication log for the write responsive to determining that the write is directed to the source logical device configured for asynchronous remote replication and that the first content has not been replicated. Responsive to the first content not being in cache, the first content can be retrieved using the reference to a storage location storing the first content. The reference can be obtained from the replication log entry or the replication queue entry.Type: GrantFiled: April 18, 2022Date of Patent: January 16, 2024Assignee: Dell Products L.P.Inventors: Vladimir Shveidel, Vamsi K. Vankamamidi
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Patent number: 11861180Abstract: A memory system includes a plurality of non-volatile memory chips and a controller configured to communicate with a host and control the plurality of non-volatile memory chips. The controller is configured to write a data frame that includes write data and a first parity for error detection and correction of the write data into first memory chips of the non-volatile memory chips in a distributed manner. The first memory chips includes N (N is a natural number of two or more) memory chips. The controller is configured to write a second parity for restoring data stored in one of the N first memory chips using data read from the other N?1 of the N first memory chips, into a second memory chip of the non-volatile memory chips that is different from any of the first memory chips.Type: GrantFiled: February 24, 2022Date of Patent: January 2, 2024Assignee: Kioxia CorporationInventor: Akiyuki Kaneko
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Patent number: 11860781Abstract: A write cleaner circuit can be used to implement write-through (WT) functionality by a write-back (WB) cache memory for updating the system memory. The write cleaner circuit can intercept memory write transactions issued to the WB cache memory and generate clean requests that can enable the WB cache memory to send update requests to corresponding memory locations in the system memory around the same time as the memory write transactions are performed by the WB cache memory, and clear dirty bits in the cache lines corresponding to those memory write transactions.Type: GrantFiled: May 4, 2022Date of Patent: January 2, 2024Assignee: Amazon Technologies, Inc.Inventors: Moshe Raz, Guy Nakibly, Gal Avisar
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Patent number: 11853099Abstract: While a connection between a copy pair comprising a primary volume in a first storage system associated with a primary host and a secondary volume in a second storage system associated with a secondary host is disconnected, systems and methods described herein can involve changing a state of the copy pair for each of the primary volume and the secondary volume to a temporary suspended state; detecting whether a network connection has recovered; for the detecting indicative of the network connection having recovered, changing the state of the copy pair for the each of the primary volume and the secondary volume to a copy pair state; and for the detecting indicative of the network connection not being recovered after a threshold period of time has elapsed, changing the state of the copy pair for the each of the primary volume and the secondary volume to a suspended state.Type: GrantFiled: May 12, 2022Date of Patent: December 26, 2023Assignee: HITACHI, LTDInventor: Tomohiro Kawaguchi
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Patent number: 11853588Abstract: A method includes: receiving, at a cluster controller of a first cluster, a request for pairing a first datastore of the first cluster to a second datastore of a second cluster, wherein each of the first cluster and the second cluster includes a plurality of datastores; determining whether the first datastore is available for pairing; in response to determining that the first datastore is available for pairing, generating an entry in a mapping table indicating that the first datastore is paired with the second datastore; receiving information associated with the second datastore; and in response to receiving the information, storing the information in the first datastore. The second cluster performs similar operations as those performed by the first cluster to achieve a bidirectional reservation between the first cluster and the second cluster.Type: GrantFiled: September 28, 2022Date of Patent: December 26, 2023Assignee: CISCO TECHNOLOGY, INC.Inventors: Geetha Srikantan, Vishwas Srinivasan, Suman Saha
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Patent number: 11847354Abstract: A sliding window cache can be used for data storage in a data grid. For example, a computing device can receive a request from a client device for storing a data entry in a data grid. The computing device can store the data entry in a first data set including a plurality of data entries distributed across a plurality of nodes of the data grid. The computing device can also store the data entry in a second data set in a sliding window cache that is embedded in the data grid. The second data set can include a subset of the plurality of data entries synchronized with the plurality of data entries of the first data set. The computing device can determine a statistic measurement associated with the sliding window cache and output the statistic measurement to the client device.Type: GrantFiled: March 17, 2022Date of Patent: December 19, 2023Assignee: RED HAT, INC.Inventors: Vittorio Rigamonti, Tristan Tarrant
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Patent number: 11847021Abstract: An operation method of memory device, comprising: selecting a target block for performing an error correction operation; reading the target block row by row; transmitting the read data to an error correction circuit; and checking and correcting read data to generate a corrected data.Type: GrantFiled: February 25, 2022Date of Patent: December 19, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Yu Lin, Feng-Min Lee
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Patent number: 11847344Abstract: A base die is configured to receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on the first data to generate a second encoded data, and transmit a second data to a memory die in the writing phase, where the second data includes the first data, the first encoded data, and the second encoded data. The base die is further configured to receive the second data from the memory die in a reading phase, perform a first error checking and correction processing on the first data and the second encoded data, and transmit a third data in the reading phase.Type: GrantFiled: May 1, 2022Date of Patent: December 19, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Shu-Liang Ning
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Patent number: 11842067Abstract: A memory controller includes a read operation controller, an error correction circuit, and a read voltage controller. The read operation controller controls a memory device to read pieces of data from a selected page of the memory device by read voltages having different levels. The error correction circuit determines fail bit numbers of the pieces of data. The read voltage controller selects a reference voltage variation from among voltage variations included in a first read voltage table, based on an erase write cycle count of the memory device, and a reference fail bit number indicating a largest fail bit number of the fail bit numbers, and adjusts a level of each of the read voltages based on the reference voltage variation and a ratio value of a corresponding one of the fail bit numbers to the reference fail bit number.Type: GrantFiled: March 9, 2022Date of Patent: December 12, 2023Assignee: SK hynix Inc.Inventor: Jong Soon Leem
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Patent number: 11842063Abstract: Software defined storage service (SDS) provides users with remote data volumes spread across multiple storage nodes across multiple failure domains. A distributed volume may be spread across replicas (e.g., failure domains), each replica having a number of partitions stored on storage nodes associated with a particular failure domain. In the event of a node failure, a partition stored on the failed node may be dynamically moved and remapped to another node in the same failure domain or within another failure domain that is different from a failure domain that includes a partition that is complementary to the partition stored on the failed node. The partition move and remapping may be transparent to a user. A partition move may occur while a distributed volume is in use by a client device or in an idle (e.g., offline) mode.Type: GrantFiled: March 25, 2022Date of Patent: December 12, 2023Assignee: EBAY INC.Inventors: Sami Ben Romdhane, Sakib Md Bin Malek, Tariq Mustafa, Jiankun Yu
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Patent number: 11829644Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: receiving a read command from a host system; in response to a first physical erasing unit being a first type physical unit, sending a first operation command sequence to instruct a rewritable non-volatile memory module to read a first physical programming unit based on a first electronic configuration; and in response to the first physical erasing unit being a second type physical unit, sending a second operation command sequence to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a second electronic configuration. The first electronic configuration is different from the second electronic configuration.Type: GrantFiled: January 22, 2022Date of Patent: November 28, 2023Assignee: PHISON ELECTRONICS CORP.Inventors: Po-Cheng Su, Chih-Wei Wang, Yu-Cheng Hsu, Wei Lin
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Patent number: 11829608Abstract: A resynchronization operation (300) adapts according to activity histories (148) within a storage platform (100). An owner node (A) and a backup storage node (B) may track activity such as the IO operations begun and use recent activity to determine respective amounts of data the owner (A) and backup (B) can expect to process without unacceptably degrading storage services. The owner (A) transfer resynchronization data in chunks, each having a size limited by the current amounts the owner (A) and backup (B) determined from current activity. When activity is low or idle, large chunks may be sent to quickly complete resynchronization, while a busy system uses smaller chunks such that the system performance is not adversely affected.Type: GrantFiled: March 15, 2022Date of Patent: November 28, 2023Assignee: Nebulon, Inc.Inventors: Siamak Nazari, Anil Swaroop, Srinivasa Murthy
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Patent number: 11822807Abstract: A method of replication in a distributed storage system, performed by the distributed storage system is provided. The method includes managing a first index for data or metadata in a first storage system, the first storage system having a first partitioning scheme. The method includes managing a second index for data or metadata in a second storage system, the second storage system having a second partitioning scheme. The method includes replicating the data or metadata from the first storage system to the second storage system, translating an identifier of the data or metadata from the first storage system, and mapping the replicated data or metadata into the second partitioning scheme, via the translating of the identifier of the data or metadata from the first storage system.Type: GrantFiled: February 10, 2022Date of Patent: November 21, 2023Assignee: PURE STORAGE, INC.Inventors: Richard A. Hankins, Igor Ostrovsky, John Colgrove, Cary A. Sandvig, Ronald Karr, Victor Yip, Zong Miao, Abhishek Jain
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Patent number: 11816340Abstract: Techniques are provided for increasing resiliency of IO operations to network interruptions. One method comprises, in response to a failure of a given IO operation on a first path between at least one initiator of a host device and at least one storage target of a storage volume of a distributed storage system, resending the given IO operation on a second path between the at least one initiator and the at least one storage target; and, in response to a completion of the given IO operation on a given one of the first path and the second path, initiating a remapping of the storage volume. The remapping of the storage volume may comprise unmapping the storage volume and mapping the storage volume. One or more IO operations having an older generation number than the generation number of the storage volume may be discarded.Type: GrantFiled: February 28, 2022Date of Patent: November 14, 2023Assignee: Dell Products L.P.Inventors: Tal Abir, Oshri Adler
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Patent number: 11809272Abstract: A computer-implemented method and a serially-attached memory device for performing the method are provided. The method includes a memory device controller receiving data over an error-protected serial link from a host processor, wherein the memory device controller is included in a serially-attached memory device along with memory media coupled to the memory device controller. The method further includes the memory device controller storing the received data in the memory media coupled to the memory device controller, the memory device controller calculating error correction code for the received data, and the memory device controller storing the error correction code in the memory media coupled to the memory device controller.Type: GrantFiled: March 17, 2022Date of Patent: November 7, 2023Inventor: Jonathan Hinkle
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Patent number: 11789766Abstract: Disclosed herein are systems and method for selectively restoring a computer system to an operational state. In an exemplary aspect, the method may include creating a backup image of the computer system comprising a set of data blocks, detecting that the computer system has begun an initial startup, identifying a subset of the data blocks read from a disk of the computer system during the initial startup. In response to determining that the computer system should be restored, the method may include restoring the subset of the data blocks such that the computer system is operational during startup, and restoring a remaining set of the data blocks from the backup image after the startup of the computer system.Type: GrantFiled: December 8, 2021Date of Patent: October 17, 2023Assignee: Acronis International GmbHInventors: Alexey Sergeev, Anton Enakiev, Vladimir Strogov, Serguei Beloussov, Stanislav Protasov
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Patent number: 11789864Abstract: A method of operating a Solid-State Drive (SSD) includes determining optimized thresholds of each corresponding segments according to their frequency of use, and executing a flush operation to write the one of the corresponding segments into a memory device according to the optimized thresholds of the corresponding segments.Type: GrantFiled: May 26, 2022Date of Patent: October 17, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Lei Zhang, Keke Ding, Li Wei Wang