Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to store a plurality of codewords in the memory device. Each codeword of the plurality of codewords includes host data and parity data corresponding to the host data. Less than all of the plurality of codewords further includes statistics corresponding to the host data. Each statistic of the plurality of codewords is the same or different as another statistic of the plurality of codewords. The statistics are either incremental statistics, adaptive statistics, or both incremental statistics and adaptive statistics.

Abstract: A system for shutting down a process of a database is provided. In some aspects, the system performs operations including tracking, during startup of a process, code locations of a process in the at least one memory. The operations may further include tracking, during runtime of the process and in response to the tracking the code locations, memory segments of the at least one memory allocated to the process. The operations may further include receiving an indication for a shutdown of a process. The operations may further include waking, in response to the indication, at least one processing thread of a plurality of processing threads allocated to a database system. The operations may further include allocating a list of memory mappings to the plurality of processing threads. The operations may further include freeing, by the first processing thread, the physical memory assigned to the processing thread by the memory mappings.

Abstract: Disclosed herein are related to an age detector for determining an age of a memory block, and a method of operation of the age detector. In one configuration, a memory system includes a memory block and an age detector coupled to the memory block. In one aspect, the memory block generates a first set of data in response to a first power on, and generates a second set of data in response to a second power on. In one configuration, the age detector includes a storage block to store the first set of data from the memory block, and inconsistency detector to compare the first set of data and the second set of data. In one configuration, the age detector includes a controller to determine an age of the memory block, based on the comparison.

Abstract: A service, responsive to a request, determines a scope that includes a specific tenant and a specific component. The service is extensible through addition of different components to manage different data sources used by different services that contribute to a set of one or more multi-tenant cloud services. The service also determines, for the specific component, parameters usable to identify the specific tenant and a specific storage path. Each of the components, responsive to being called to perform a backup or restore with a current set of parameters, is to be implemented to cause data, which belongs to a currently identified tenant, to be copied between the respective one of the data sources and a backup store according to a currently identified storage path. The service also calls the specific component to perform the backup or restore with the parameters.

Abstract: A reference snapshot selection technique is configured to select a reference snapshot resolution algorithm used to determine an appropriate reference snapshot that may be employed to perform incremental snapshot replication of workload data between primary and secondary sites in a data replication environment. A reference resolution procedure is configured to process a set of constraints from the data replication environment to dynamically select the reference snapshot resolution algorithm based on a figure of merit that satisfies administrative constraints to reduce or optimize resource utilization in the data replication environment.

Abstract: Apparatus and methods are disclosed, including providing available data operations for the storage system processor to a host processor, identifying data operations to be performed by the storage system processor, and assigning identified data operations to the storage system processor to reduce bus traffic between the host processor and the storage system processor, to improve host processor performance, and to reduce energy use by the host processor.

Abstract: A computer program product and a data storage device including first and second storage controllers operating in active-passive mode with a shared disk. Each storage controller includes a storage device storing program instructions and a processor to process the program instructions and perform various operations. The operations include receiving a task to be performed by the storage device containing the first and second storage controllers, wherein the first storage controller is currently operating as an active storage controller and the second storage controller is currently operating as a passive storage controller. The operations further include determining whether the received task has a high priority or a low priority, performing the received task in response to determining that the received task has a high priority, and delegating the received task to the second storage controller for performance in response to determining that the received task has a low priority.

Abstract: Disclosed herein are systems and method for selectively restoring a computer system to an operational state. In an exemplary aspect, the method may create a backup image of the computer system comprising a set of data blocks, and create and start a virtual machine based on the backup image. The method may identify a subset of the data blocks accessed from the backup image during startup of the virtual machine. In response to determining that the computer system should be restored, the method may restore the subset of the data blocks such that the computer system is operational during startup, and restore a remaining set of the data blocks from the backup image after the startup of the computer system.

Abstract: A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The processing device further receives a request to perform a read operation on data stored on the wordline and sub-block of the memory array, sends a suspend command to the memory device to cause the memory device to suspend the program operation, reads data corresponding to the read operation from a page cache of the memory device, and sends a resume command to the memory device to cause the memory device to resume the program operation.

Abstract: The present invention provides a control method of a flash memory controller wherein the control method includes the steps of: selecting a first block; reading pages of the first block and determining a bit error rate or a bit error count of each page; for each of the pages, if the bit error rate or the bit error count of the page is not greater than a first threshold value, moving the data of the page into a second block; and for each of the pages, if the bit error rate or the bit error count of the page is greater than the first threshold value, moving the data of the page into a third block; wherein a number of pages corresponding to a word line of the second block is less than a number of pages corresponding to a word line of the third block.

Abstract: Disclosed herein are a hybrid memory management apparatus and method for an many-to-one virtualization environment. The hybrid memory management apparatus is implemented in an inverse-virtualization-based multi-node computing system including multiple physical nodes, each containing hybrid memory in which DRAM and NVRAM coexist, a virtual machine, and hypervisors, and includes memory for storing at least one program, and a processor for executing the program, wherein the program includes a remote request service module for processing a page-related request with reference to the hybrid memory and responding to the page-related request by transmitting a result of processing, an internal request service module for processing an internal page fault request with reference to a hybrid memory and responding to the internal page fault request, and a data arrangement module for responding to an inquiry request for a location at which a newly added page is to be arranged in the hybrid memory.

Abstract: Systems and methods for adaptive fetch coalescing are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The host device notifies the memory device, via a doorbell update, of commands on the submission queue. Instead of fetching the command responsive to the doorbell update, the memory device may analyze one or more aspects in order to determine whether and how to coalesce fetching of the commands. In this way, the memory device may include the intelligence to coalesce fetching in order to more efficiently fetch the commands from the host device.

Abstract: In some examples, performance counters for computer memory may include ascertaining a request associated with a memory address range of computer memory. The memory address range may be assigned to a specified performance tier of a plurality of specified performance tiers. A performance value associated with a performance attribute of the memory address range may be ascertained, and based on the ascertained performance value, a weight value may be determined. Based on the ascertained request and the determined weight value, a count value associated with a counter associated with the memory address range may be incremented. Based on an analysis of the count value associated with the counter, a determination may be made as to whether the memory address range is to be assigned to a different specified performance tier of the plurality of specified performance tiers.

Abstract: In general, embodiments of the invention relate tracking the operating temperature of the solid-state memory modules (SSMMs) in order to improve their performance.

Abstract: A method begins by a processing module receiving a request to store a data object in distributed storage (DS) units. The processing module generates and transmits a proposal message that includes a preferred source name, and a proposal attempt identifier to a plurality of DS units. The processing module then receives a proposal message acceptance response from at least one of the plurality of DS units and when the proposal message response indicates that no other proposal messages have been received by at least one of the plurality of DS units, retains the preferred source name included within the proposal message as a persistent value for the source name.

Abstract: Data units are stored in private caches in nodes of a multiprocessor system, each node containing at least one processor (CPU), at least one cache private to the node and at least one cache location buffer (CLB) private to the node. In each CLB location information values are stored, each location information value indicating a location associated with a respective data unit, wherein each location information value stored in a given CLB indicates the location to be either a location within the private cache disposed in the same node as the given CLB, to be a location in one of the other nodes, or to be a location in a main memory. Coherence of values of the data units is maintained using a cache coherence protocol. The location information values stored in the CLBs are updated by the cache coherence protocol in accordance with movements of their respective data units.

Abstract: The invention relates to a data processing system and a date processing method. The data processing system is configured to perform a hardware transactional memory (HTM) transaction. The data processing system comprises a byte-addressable nonvolatile memory for persistently storing data and a processor being configured to execute an atomic HTM write operation in connection with committing the HTM transaction by writing an indicator to the nonvolatile memory indicating the successful commit of the HTM transaction.

Abstract: Devices and techniques for communicating a programmable atomic operator to a memory controller are described herein. A memory controller can receive a memory request and extract a command indicator that indicates a programmable atomic operator (PAO) command from the memory request. The memory controller can then extract a PAO index from the request and invoke the PAO based on the PAO index.

Abstract: A storage system with several integrated components and method for use therewith are provided. In one embodiment, a storage system comprising: a plurality of non-volatile memory devices; a controller in communication with the plurality of non-volatile memory devices; a plurality of data buffers in communication with the controller and configured to store data sent between the controller and an input/output bus; and a command and address buffer configured to store commands and addresses sent from a host, wherein the command and address buffer is further configured to synchronize data flow into and out of the plurality of data buffer; wherein at least three of the above components are integrated with each other.

Abstract: The subject matter of this specification can be implemented in, among other things, a method including creating a new disk file at a reference point-in-time, wherein an original disk file is a backing file of the new disk file, copying the original disk file to a disk snapshot file, in response to the original disk file being copied to the disk snapshot file, merging the original disk file and the new disk file to form a merged file, wherein a virtual machine is to continue to perform disk operations using the merged file, and determining whether the merged file is synchronized with the original disk file and the new disk file by determining whether entries of a bitmap for the merged file match corresponding entries of a bitmap for the new disk file.