Abstract: A device encodes data using Mojette Transform to a block device configuration, in order to generate encoded data. The device transmits the data to other devices. The other devices store the received information. The data stored in the other devices can be efficiently updated using partial update.

Abstract: Certain aspects of the present disclosure provide techniques for a multi-user data packet, such as a physical downlink shared channel (PDSCH) packet. A method by a base station (BS) includes sending a control channel, such as physical downlink control channel (PDCCH), scheduling a plurality of user equipment (UEs) for a data packet transmission and sending data for the plurality of UEs in a single transport block on the scheduled data packet. The UE receives the control channel and data packet, and determines the data in the multi-user data packet that is intended for the UE.

Abstract: A memory system includes a memory medium, a loop-buffer configured to store read data outputted from the memory medium in a first operation mode, a fake-command generator configured to generate a fake-command in a second operation mode, and an error correction code (ECC) decoder configured to perform an ECC decoding operation of the read data stored in the loop-buffer in response to the fake-command.

Abstract: An encoding method includes: receiving, by an encoder, an information for encoding; generating, by the encoder, a first portion codeword according to a first encoding rule and the information for encoding, wherein the first encoding rule is an encoding rule configured to generate LDPC code; generating, by the encoder, a second portion codeword according to a second encoding rule different from the first encoding rule and a double check region of the first portion codeword; and concatenating, by the encoder, the first portion codeword and the second portion codeword to generate a codeword. A plurality of trapping sets corresponding to the first encoding rule include at least one error bit within the double check region.

Abstract: A method comprises receiving information on a selected redundancy version at a user device. The redundancy version is associated with block coding. The block coding may be LDPC. The method may comprise using the information when communicating with a base station. The position of the redundancy version may satisfy one or more criteria.

Abstract: A system and method for performing scan chain testing is disclosed. Scan cells, in the form of scan chains, are inserted into circuit designs for testing those circuit designs. The integrity of the scan chains is checked for defects before testing the circuit under test. In order to do so, various scan chain patterns, including one or both of U-turn and Z-turn patterns, are used in order to generate scan chain test data. The scan chain test data is analyzed in order to identify one or both of a type of defect (e.g., a timing fault, stuck-at fault, etc.) or a location of the defect. Further, the scan chain testing is performed using chain patterns with adaptive length.

Abstract: To improve communication performance such as a throughput and communication efficiency in a system where multiple communication schemes are used. An apparatus includes a transmitter configured to transmit a transmit signal generated from transmission bits, the transmitter including a coding unit configured to generate the transmission bits by coding and rate matching, the coding unit including a first coding unit, a first interleaving unit, a first bit selection unit, a second coding unit, a second interleaving unit, and a second bit selection unit. The first bit selection unit and the second bit selection unit are different in the initial position based on the same redundancy version.

Abstract: In some aspects, methods and apparatus for wireless communications are configured to generate a packet for wireless communication where the packet includes a mark symbol in a preamble of the packet where the mark symbol includes a signature or stamp field in the mark to provide protocol information that indicates the protocol of the packet, such as an 802.11 EHT packet. In some other aspects, a cyclic redundancy check field in the mark symbol may be manipulated in various ways to indicate the protocol of the packet in lieu of providing the signature or stamp field.

Abstract: A system including a user interface, a memory, and a processor configured to perform operations including receiving memory scrambling information including address scrambling information and data scrambling information, and associating one or more address bus bits of a plurality of address bus bits with an address grouping of a plurality of address groupings based on the address scrambling information is disclosed. In an embodiment, the address grouping corresponds to at least one address segment of a plurality of address segments. The operations include determining an error correction code for the at least one address segment that includes one or more address check bits. The operations include generating a physical layout of memory components based on the memory scrambling information. The memory components include at least one of the plurality of address bus bits, and the one or more address check bits.

Abstract: A method and an apparatus for controlling an interleaving depth are provided. The interleaving depth controlling method includes performing a modulo operation on an interleaving depth selected to be less than or equal to a maximum interleaving depth and a total number of codewords to obtain a number of remaining codewords; and comparing the total number of the codewords to the interleaving depth, when the number of the remaining codewords excludes “0”, to control the interleaving depth.

Abstract: Some instances of a memory device include a memory die having an array of memory cells including a plurality of banks. In some cases, the memory die further includes a first error correcting code (ECC) circuit coupled with a first bank of memory cells, where the first ECC circuit is configured to perform operations associated with a first access operation (e.g., write operation) of the first bank of memory cells. In some examples, the memory die further includes a second ECC circuit coupled with the first bank of memory cells, where the second ECC circuit is configured to perform ECC operations associated with a second access operation (e.g., read operation) of the first bank. In some cases, the first ECC circuit is located under the footprint of the array and the second ECC circuit is located outside the footprint of the array.

Abstract: A semiconductor memory system includes: a semiconductor memory device to store a codeword; and a low-density parity check (LDPC) decoder to decode the codeword, based on a parity check matrix, to generate a decoded codeword, wherein the LDPC decoder includes: a selector to select one or more sub-matrices that share the same layer index of the parity check matrix, and select variable nodes corresponding to columns included in the selected one or more sub-matrices based on a threshold value and a number of unsatisfied check nodes (UCNs) connected to the selected variable nodes; a variable node updater to update decision values of variable nodes corresponding to all columns included in the parity check matrix; a syndrome checker to determine whether decoding the codeword has been performed successfully or not; and a check node updater to update a backup syndrome, the threshold value, and a size of a processing unit.

Abstract: A disclosed apparatus and method reduce the likelihood of multiple bit single event upset (SEU) errors in space-deployed memory devices and memory macros. For each memory, a bit selection layer effectively increases the mux of the memory bit table, thereby reducing the word size while increasing the word capacity, without changing the total memory capacity. As a result, the separation between the physical bit storage locations for each word is increased, thereby reducing the likelihood of multiple bit SEU errors. A buffer can be implemented if the memory lacks individual bit write control. The memory can be implemented in a core integrated circuit (IC) of an multi-chip module (MCM) hybrid integrated circuit (HIC), and the bit selection layer and/or buffer can be implemented in a chiplet or chiplets of the MCM-HIC.

Abstract: Compression coding may be used with forward error correction (FEC) coding to provide higher information rates by reducing the proportion of redundant bits relative to information bits that are transmitted from a transmitter to a receiver. In one example, first determiners and second determiners are calculated from a set of information bits, where each first determiner is calculated from a different first subset of the information bits along a first dimension, and each second determiner is calculated from a different second subset of the information bits along a second dimension that differs from the first dimension. First and second nubs are calculated from the first and second determiners, respectively, each nub comprising a number of redundant bits that is less than the number of bits in the determiners from which the nub is calculated. The information bits and the nubs are transmitted over one or more communications channels.

Abstract: An information processing apparatus including a control unit that performs control for adding, to request information for requesting a different apparatus for a confirmation response to a plurality of data transmitted to the different apparatus, notification information. The notification information is information regarding at least sequence numbers other than a start sequence number from among sequence numbers corresponding to the plurality of data. Further, the control unit transmits the request information, to which the notification information is added, to the different apparatus.

Abstract: A processing device receives a request to locate a first distribution edge at a target bit error rate (BER) of a first programming distribution. The processing device measures a first BER sample of the first programing distribution using a first offset value that is offset from a first center value corresponding to a first read level threshold and a second BER sample using a second offset value that is offset from the first offset value. The processing device determines that the second BER sample exceeds the target BER and the first BER sample does not exceed the target BER. The processing device determines a first location of the first distribution edge by interpolating between the first BER sample and the second BER sample.

Abstract: Disclosed is a system comprising a memory component and a processing device operatively coupled with the memory component, to provide, to a host system, geometric parameters of the memory component, receive, from the host system, a first data to be stored in the memory component, execute a first write operation to program the first data into the memory component, detect that the first write operation has failed, provide a failure notification to the host system, wherein the failure notification comprises an indication of a range of memory cells storing, after the first write operation, incorrect data, and receive, from the host system, a second data to be stored in the memory component, in response to the host system identifying, based on the geometric parameters and the failure notification, a range of logical addresses of the memory component corresponding to the range of memory cells storing incorrect data.

Abstract: A method includes: obtaining a first sequence corresponding to a basic code length N0; determining N to-be-encoded bits, where the N to-be-encoded bits include N2 fixed bits, and N is greater than the basic code length N0; extending the first sequence to obtain a second sequence; determining locations of the N2 fixed bits in the N to-be-encoded bits based on polar channel serial numbers indicated by first N2 elements in the second sequence; and performing polar encoding on the N to-be-encoded bits to obtain encoded bits. The locations of the fixed bits in the N to-be-encoded bits are determined based on the second sequence, and the second sequence is obtained by extending the first sequence corresponding to the basic code length N0.

Abstract: A check node update processor of the low density parity check (LDPC) code decoder includes: an approximate first minimum (AFM) condition check unit which checks whether a predetermined specific condition is satisfied, and a check node determining unit which sets an approximate minimum value as a size of an entire check node output when it is determined that the specific condition is satisfied as a checking result in the AFM condition check unit and calculates a first minimum value as a true minimum value and sets a second minimum value as an approximate minimum value when it is determined that the specific condition is not satisfied to determine a size of the check node output.

Abstract: Fault-tolerant error correction (EC) is desirable for performing large quantum computations. In this disclosure, example fault-tolerant EC protocols are disclosed that use flag circuits, which signal when errors resulting from ? faults have weight greater than ?. Also disclosed are general constructions for these circuits (also referred to as flag qubits) for measuring arbitrary weight stabilizers. The example flag EC protocol is applicable to stabilizer codes of arbitrary distance that satisfy a set of conditions and uses fewer qubits than other schemes, such as Shor, Steane and Knill error correction. Also disclosed are examples of infinite code families that satisfy these conditions and analyze the behaviour of distance-three and -five examples numerically. Using fewer resources than Shor EC, the example flag EC protocols can be used in low-overhead fault-tolerant EC protocols using large low density parity check quantum codes.