Abstract: A test device and method with built-in self-test logic and a communication device. The test device includes at least one generator and at least one checker which are disposed between a physical layer and a medium access control layer. The at least one generator is configured to generate a protocol pattern to form a data path between the physical layer and the medium access control layer, and generate different pseudo random bit sequence patterns in the data path. The at least one checker is configured to test a data stream in the physical layer and/or the medium access control layer according to the pseudo random bit sequence patterns, thereby locating a fault position.

Abstract: An erasure code (EC)-based data processing method implemented by a storage controller includes obtaining K data chunks, dividing each of the K data chunks into two data slices, encoding the 2*K data slices based on a parity matrix including 2*M rows and 2*(K+M) columns of elements, to obtain 2*M parity slices, and separately storing the K data chunks and the M parity chunks in different storage devices.

Abstract: Methods, systems, and devices for targeted command/address parity low lift are described. A memory device may receive a command (e.g., a write command or a read command) from a host device over a first set of pins and may perform data transfer over a second set of pins with the host device during a set of time intervals according to the command. The memory device may exchange a parity bit associated with the command with the host device over a third set of pins during a first time intervals of the set of time intervals. In some cases, the third memory device may exchange at least one additional bit associated with the command with the host device during at least one time interval of the set of time intervals.

Abstract: A system with multiple processing domains sharing a memory resource accessed via a shared memory controller detects a memory error. As data is written to the shared memory resource, each processing domain generates a diagnostic code as a function of the data, the memory address for the data, and of a unique identifier corresponding to the processing domain. The diagnostic code is stored with the data for verification when the data is read back. As the data is read back, the processing domain separates the diagnostic code from the data being read and generates another diagnostic code in the same manner as the original diagnostic code. The other diagnostic code is compared to the initial diagnostic code. If both diagnostic codes are the same, the processing domain can be confident that the data read from the shared memory resource is the same as the data that was originally written.

Abstract: A method includes transmitting an ECC encoded first data and an ECC encoded second data from a memory to a logic circuit, and generating an ECC encoded output data by executing an ECC-Space operation using the ECC encoded first data as a first operand and the ECC encoded second data as a second operand. The ECC encoded first data and the ECC encoded second data are the corresponding results of encoding a first data and a second data with an ECC algorithm. The ECC-Space operation is translated from a two operands operation that is operative to transform the first data and the second data into a third data. The ECC encoded output data is identical to a result of encoding the third data with the ECC algorithm if the third data is encoded with the ECC algorithm.

Abstract: One example aspect of the techniques discussed herein is a User Equipment (UE) comprising processing circuitry configured to determine one or more thresholds for code block segmentation, wherein the one or more thresholds for code block segmentation comprise one or more of a payload threshold (Kseg) or a code rate threshold (Rseg); determine to perform code block segmentation based on the one or more thresholds and at least one of a current payload (K) of an information block or a current code rate (R) for the information block; segment the information block into a plurality of segments; and encode each segment of the plurality of segments via a polar encoder with a code size (N).

Abstract: Methods, devices, and systems for testing a number of combinations of memory in a computer system. A modular memory device is installed in a memory channel in communication with a processor. The modular memory device includes a number of memory storage devices. The number of memory storage devices include a number of pins. A subset of the number of memory storage devices is selected. A subset of the plurality of pins which do not correspond to the subset of the number of memory storage devices and are not part of a memory map of the computer system is selected. Each pin of the subset of the plurality of pins configured with a termination impedance. The subset of the number of memory storage devices is tested.

Abstract: Rebalancing as a result of re-encoding a code chunk in response to scaling out of a geographically diverse storage system employing erasure coding technology is disclosed. After a scaling out event, a new erasure coding scheme can be selected. An old coding chunk generated according to an old erasure coding scheme can be re-encoded into a new coding chunk according to the new erasure coding scheme and based on a data chunk not previously protected by the old coding chunk. The re-encoding can be selected to diversify distribution of chunks, resulting in rebalancing occurring as part of re-encoding. In an embodiment, the new coding chunk can be generated in a new zone from the scaling out event. In another embodiment, the data chunk can be moved to the new zone from the scaling out event.

Abstract: Methods and devices are provided for error correction of distributed data in distributed systems using Reed-Solomon codes. In one embodiment, processes are provided for error correction that include receiving a first correction code for data fragments stored in storage nodes, constructing a second correction code responsive to an unavailable storage node of the storage nodes, performing erasure repair of the unavailable storage node, and outputting a corrected data fragment. The first correction code is a Reed-Solomon code represented as a polynomial and the second correction code is represented as a second polynomial with an increased subpacketization size. Processes are configured to account for repair bandwidth and sub-packetization size. Code constructions and repair schemes accommodate different sizes of evaluation points and provide a flexible tradeoff between the subpacketization size repair bandwidth of codes.

Abstract: A memory controller controlling an operation of a memory device includes a parity module configured to perform one or more exclusive OR operations using data to be stored in the memory device and generate parity according to the one or more exclusive OR operations, and a recovery controller configured to control the parity module to store the parity in the memory device based on the number of times the exclusive OR operation is performed.

Abstract: A method performed at an electronic device comprises receiving information bits, a first nub, and a second nub, each nub comprising redundant values; calculating first calculated determiners from first subsets of the information bits along a first dimension; calculating first corrected determiners by applying first FEC decoding to a combination of the first calculated determiners and the first nub; correcting at least one error in the information bits using a difference between the first corrected determiners and the first calculated determiners; calculating second calculated determiners from second subsets of the information bits along a second dimension that differs from the first dimension; calculating second corrected determiners by applying second FEC decoding to a combination of the second calculated determiners and the second nub; and correcting at least one additional error in the information bits using a difference between the second corrected determiners and the second calculated determiners.

Abstract: A semiconductor device of an embodiment includes an ECC decoding processing circuit configured to perform ECC decoding on ECC frame data in a lateral direction of a product code frame, an RS decoding processing circuit configured to perform Reed-Solomon (RS) decoding on second frame data in a longitudinal direction of the product code frame, a memory M0 in which a syndrome generated for the ECC frame data decoded is stored, a memory M1 in which an RS syndrome generated for ECC frame data for which the ECC decoding has been successful is stored, and a memory D in which ECC frame data for which the ECC decoding has been failed is stored as frame data which cannot be corrected through decoding, and frame collection processing, and iterative correction processing of performing RS decoding on the uncorrected frame data collected in the frame collection processing are executed.

Abstract: A system for performing a scan test of a processor core includes a scan test module and a processor including a processor core and an input/output die, where the input/output die is coupled to the processor core. The scan test module transmits, in parallel to the input/output die, scan test input data. A serializer/deserializer module of the input/output die receives the input data, serializes the input data, and transmits the serialized input data to the processor core. A serializer/deserializer module of the processor core receives the serialized scan test input data, deserializes the input data, receives result data generated in dependence upon the input data, serializes the result data, and transmits the serialized result data to the input/output die. The input/output die serializer/deserializer module receives the result data, deserializes the result data, and provides the result data to the scan test module. Error detection can be carried out through redundancy.

Abstract: An operating method of a memory controller to update metadata using journaling data in a short time during a booting operation, and to maintain reliability of the updated metadata. The operating method of a memory controller includes loading metadata into sub-regions of a buffer memory, updating the metadata using journaling data in a state that error correction code (ECC) functions of memory controller for the sub-regions are disabled, generating a first parity data of data stored in the first sub-region, and enabling the ECC function of the first sub-region, after the first parity data is generated.

Abstract: A data storage system includes a plurality of data blocks. A set of data blocks are protected by an erasure correcting code and each of the data blocks in the set of data blocks includes block identification information. The data storage system includes a processor and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. The logic is configured to verify the block identification information for each of the data blocks in the set of data blocks at the time of read and, as part of reconstructing a data block, reconstruct the block identification information for the reconstructed data block, and verify the block identification information.

Abstract: Aspects of this disclosure provide a technique for implementing polar encoding with incremental redundancy HARQ re-transmission. In particular, a transmitter encodes a message using different polar codes to obtain a first codeword and a second codeword that is twice the length of the first codeword, and transmit the first codeword as an original transmission, and the second half of the second codeword as a re-transmission without transmitting the first half of the second codeword. Information bits that are common to both the first codeword and the second half of the second codeword is mapped to more-reliable bit-locations in the second half of the second codeword. Decoded bit values for the common information in the original transmission and retransmission is compared by the receiver to perform a parity check.

Abstract: A testing device for memory includes a memory array and a test apparatus. The test apparatus includes a controller and a pattern generator. The pattern generator generates a background data, a first pattern data, and a second pattern data. The controller sets up the background data to a to-be-tested memory sub-array of the memory sub-arrays, performs a first memory test operation with the to-be-tested memory sub-array according to the first pattern data for detecting an occurrence of a hardware failure of the to-be-tested memory sub-array is occurred during the first memory test operation. The controller performs a second memory test operation with the to-be-tested memory sub-array according to the second pattern data for detecting the occurrence of the hardware failure of the to-be-tested memory sub-array during the second memory test operation in response to the hardware failure of the to-be-tested memory sub-array is not occurred during the first memory test operation.

Abstract: A computer-implemented method, according to one embodiment, includes: selecting strips from each storage unit for a given erasure code stripe such that the given erasure code stripe includes at most one strip from a high failure rate region of the respective storage unit, where each of the storage units include high and low failure rate regions. The selected strips are organized such that a number of each strip in the given erasure code stripe is offset from the remaining strips by an amount that is greater than a total number of strips in the high failure rate regions. The organized selected strips are further mapped to form the given erasure code stripe such that the high failure rate regions on each storage unit are mapped to one or more sequentially numbered strips, and the low failure rate regions are mapped to additional sequentially numbered strips.

Abstract: A system-on-chip (SoC) is disclosed. The SoC includes a set of fake fault injection circuits and a critical intellectual property (IP) core that includes first and second control circuits. The first and second control circuits are each operable in a test mode and a functional mode. The first and second control circuits are operated in the functional mode in lockstep in an absence of a fake fault input. In a presence of the fake fault input, one of the first and second control circuits is switched from the functional mode to the test mode. One of the first and second control circuits operating the test mode generates a fake fault response for the fake fault input. The critical IP core is determined as one of error-free and erroneous based on a detection of the generated fake fault response as one of error-free and erroneous, respectively.

Abstract: A parity generation logic circuit includes a first parity generation part and a second parity generation part. The first parity generation part is configured to generate a first parity in a first error correction mode having a first error correction capability for original data. The second parity generation part is configured to generate a second parity using the first parity in a second error correction mode having a second error correction capability.