Abstract: A check node update processor of the low density parity check (LDPC) code decoder includes: an approximate first minimum (AFM) condition check unit which checks whether a predetermined specific condition is satisfied, and a check node determining unit which sets an approximate minimum value as a size of an entire check node output when it is determined that the specific condition is satisfied as a checking result in the AFM condition check unit and calculates a first minimum value as a true minimum value and sets a second minimum value as an approximate minimum value when it is determined that the specific condition is not satisfied to determine a size of the check node output.

Abstract: Fault-tolerant error correction (EC) is desirable for performing large quantum computations. In this disclosure, example fault-tolerant EC protocols are disclosed that use flag circuits, which signal when errors resulting from ? faults have weight greater than ?. Also disclosed are general constructions for these circuits (also referred to as flag qubits) for measuring arbitrary weight stabilizers. The example flag EC protocol is applicable to stabilizer codes of arbitrary distance that satisfy a set of conditions and uses fewer qubits than other schemes, such as Shor, Steane and Knill error correction. Also disclosed are examples of infinite code families that satisfy these conditions and analyze the behaviour of distance-three and -five examples numerically. Using fewer resources than Shor EC, the example flag EC protocols can be used in low-overhead fault-tolerant EC protocols using large low density parity check quantum codes.

Abstract: A transmitter and receiver of a broadcasting signal and a method of processing the broadcasting signal are provided. The transmitter includes: a segmenter configured to segment an L1 signaling of a frame into a plurality of segmented L1 signalings such that each of the segmented L1 signalings has bits a number of which is equal to or smaller than a predetermined number; and an encoder configured to perform a Bose, Chaudhuri, Hocquenghem (BCH) and a low density parity check (LDPC) encoding, or the LDPC encoding without the BCH encoding, with respect to the segmented L1 signalings.

Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach.

Abstract: A data integrity check is performed on a data block of the memory component to obtain a reliability statistic for each of a set of sampled memory cells in the data block. A distribution statistic is determined based on the reliability statistic for each of the set of sampled memory cells. A subset of the data block is identified to be relocated to another data block of the memory component based on the distribution statistic. Data of the subset of the data block is relocated to the other data block.

Abstract: One embodiment provides a system that facilitates efficient storage and retrieval using erasure coding. During operation, the system determines a finite field solution that conforms to both locality and maximum distance separable (MDS) properties of an erasure-coding system. The system determines a generator matrix of the erasure-coding system based on the finite field solution and generates, from a data element, a plurality of coded fragments based on the generator matrix of the erasure-coding system. The plurality of coded fragments includes a set of enhanced coded fragments that allows reconstruction of the data element and a set of regular coded fragments. The number of the enhanced coded fragments can be fewer than a threshold number of coded fragments for the erasure-coding system.

Abstract: A method of correcting an error in a memory array in a DRAM during a read operation, wherein the memory array includes a data array and an ECC array, the method comprising: reading data from the memory array; when the data contains one or more erroneous data bits, correcting the erroneous data bits by an ECC decoding and correcting module in the DRAM; registering only corrected erroneous data bits and their positions in a register; controlling a plurality of write drivers in the DRAM by the register so as to write only the corrected erroneous data bits back to the memory array.

Abstract: Techniques and mechanisms for determining information which is to be used for performing bit error correction. In an embodiment, bit reliability information is calculated based on a first likelihood function, and also on data signals which each indicate a respective bit of a codeword. Values of the bit reliability information each indicate, for a respective bit of the codeword, a confidence that the bit is at a particular logic state. A syndrome vector is calculated based on the bit reliability information, and one of the first likelihood function or a second likelihood function is selected based on one or more bit errors which are indicated by the syndrome vector. The selected one of the first likelihood function or the second likelihood function is used to correct bit errors of the codeword. In another embodiment, the first likelihood function is a default likelihood function to be used for initial syndrome vector calculations.

Abstract: Systems and methods are disclosed for error correction with multiple log likelihood ratio (LLR) lookup tables (LUTs) for a single read, which allows for adaptation to asymmetry in the number of 0 or 1 bit errors without re-read operations. In certain embodiments, an apparatus may comprise a circuit configured to receive a sequence of bit value estimates for data read from a solid state memory during a single read operation, generate a first sequence of LLR values by applying the sequence of bit value estimates to a first LUT, and perform a decoding operation on the first sequence of LLR values. When the first sequence of LLR values fails to decode, the circuit may be configured to generate a second sequence of LLR values by applying the bit value estimates to a second LUT, and perform the decoding operation on the second sequence of LLR values to generate decoded data.

Abstract: A method begins by a dispersed storage (DS) processing unit of a dispersed storage network (DSN) generating a hint regarding data stored or to be stored. When the data is to be stored, the DS processing module divides the data into data segments and dispersed storage error encodes a data segment of the data segments to produce a set of encoded data slices. The method continues by the DS processing unit generating a set of hints based on the hint and affiliating the set of hints with the set of encoded data slices to produce a set of affiliated encoded data slices. The method continues by the DS processing unit sending the set of affiliated encoded data slices to a set of storage units of the DSN such that a storage unit of the set of storage units stores an encoded data slice in accordance with a corresponding hint.

Abstract: Described herein is an error correction circuit that includes a syndrome check history manager configured to maintain a history of syndrome checks corresponding to one or more iterations of the iterative decoding scheme. The error correction circuit also includes a trapping set detector configured to compare a trapping set determination policy with the history of syndrome checks to determine whether the history of syndrome checks meets criteria of the trapping set determination policy, while error correction decoding is performed, and determine that a trapping set exists when the history of syndrome checks satisfies the trapping set determination policy. The trapping set determination policy is related to at least one of a change in a syndrome vector, a number of UCNs, and a change in the number of UCNs.

Abstract: The present technology relates to a transmission device, a transmission method, a reception device, and a reception method for securing good communication quality in data transmission using an LDPC code. LDPC coding for information bits with an information length K=N×r is performed on the basis of an extended parity check matrix having rows and columns each extended by a predetermined puncture length L with respect to a parity check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 14/16, so that an extended LDPC code having parity bits with a parity length M=N+L?K is generated. Then, a head of the information bits of the extended LDPC code is punctured by a puncture length L, so that a punctured LDPC code with the code length N of 69120 bits and the coding rate r is generated. The extended parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits.

Abstract: A method for data communication between a first node and a second node over a data path includes forming one or more redundancy messages from data messages at the first node using an error correcting code and transmitting messages from the first node to the second node. The transmitted first messages include the data messages and the redundancy messages. The method includes, receiving, at the first node, second messages indicative of a rate of arrival at the second node of the messages transmitted from the first node, and of successful and unsuccessful delivery of the first messages transmitted from the first node to the second node. A first transmission limit and a second transmission limit are maintained according to the received second messages. Transmission of additional messages from the first node to the second node is limited according to the first and the second transmission limits.

Abstract: A memory system includes a memory device configured to store data, and read and output the stored data in a read operation, and a memory controller configured to perform an error correction operation on the data received from the memory device in the read operation and control the memory device to perform a read retry operation, based on the result of the error correction operation. The memory device outputs the data read in the read retry operation to the memory controller when the number of specific data, among data read in the read retry operation, is in a set range. Only reliability-ensured data in the read retry operation is output to the memory controller. Thus, the number of times of outputting data to the memory controller can be decreased, and the number of times where the memory controller performs an error correction operation can be decreased.

Abstract: An error handling technique for a computing device includes detecting a memory error during execution of the program instructions to generate a computational result, and generating an error message containing information about the memory error. The error message can be stored in a notification memory space, and be made available for access, for example, by a host system. The execution of the program instructions is allowed to continue to generate the computational result despite detecting the memory error. When the computation result becomes available, a confidence level of the computational result can be determined based on which program instruction or which computational stage resulted in the memory error. The confidence level can be used to assess whether the computational result is acceptable.

Abstract: An apparatus has a control domain comprising functional circuitry to perform logical operations when in an operational state. The functional circuitry comprises at least one output and a state of the output depends on the logical operations. Domain control circuitry controls the control domain to put the functional circuitry in one of the operational state and a non-operational state. Isolation circuitry isolates the functional circuitry within the apparatus by holding the state of the output at a predetermined value when the domain control circuitry puts the functional circuitry in the non-operational state. Self-test control circuitry causes the domain control circuitry to control the control domain to put the functional circuitry in the non-operational state and to cause a self-test procedure to be carried out with respect to the functional circuitry.

Abstract: Technical solutions are described for computing data check word for a host request for an I/O processing operation at a host computer system that communicates with a control unit. An example method includes obtaining information for a first I/O operation at a channel subsystem in the host computer system, and accessing an address control word (ACW) of the first I/O operation. The ACW is stored in the local channel memory, and the ACW includes a first data check seed-value. The method also includes computing a first data check word based on the first data check seed-value from the ACW. The method also includes obtaining information for a second I/O operation at the channel subsystem, and in response to the second i/o operation corresponding to said ACW of the first I/O operation, computing a second data check word based on a second data check seed-value from a cache memory.

Abstract: The present technology relates to a transmission method and a reception device capable of ensuring good communication quality in data transmission by using an LDPC code. In group-wise interleaving, an LDPC code with a code length N of 69120 bits is interleaved in units of bit groups of 360 bits. In group-wise deinterleaving, an arrangement of the LDPC code after the group-wise interleaving is returned to an original arrangement. The present technology can be applied, for example, to the case of performing data transmission by using an LDPC code or the like.

Abstract: An error correction device includes a bit reliability value determination circuit configured to determine bit reliability values corresponding to hard decision bits, based on soft decision bit sets corresponding to the hard decision bits; and a decoder including a variable node configured to receive and store the hard decision bits and the bit reliability values, and perform a decoding operation for the hard decision bits by restoring reliability values from the bit reliability values. The reliability values correspond to elements except a decision symbol configured by the hard decision bits, in a Galois field (GF) defined in the variable node. All necessary reliability values are not transmitted to each variable node, instead, compressed reliability values are transmitted to the variable node. The variable node receives and retains the compressed reliability values, restores necessary reliability values, and uses them in a decoding operation.

Abstract: A method and apparatus for incremental RAID stripe update parity calculations. The method includes: receiving, at a first set of solid state drives, a last portion of a redundant array of independent disks (RAID) stripe among multiple portions of the RAID stripe, wherein the RAID stripe includes multiple shards, and wherein each previous portion of the RAID stripe is written to the first set of solid state drives; calculating a current parity value based on the last portion of the RAID stripe and a previous parity value updated after receiving each previous portion of the RAID stripe; and responsive to receiving all portions of a shard of the RAID stripe, copying the shard of the RAID stripe from the first set of solid state drives to a second set of solid state drives.